-
公开(公告)号：US06303432B1
公开(公告)日：2001-10-16
申请号：US09411386
申请日：1999-10-04
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/76224 , H01L21/823835 , H01L21/823878 , H01L27/10852 , H01L27/10873
摘要： There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.
摘要翻译： 描述了制造半导体器件的方法，其中在单个半导体衬底上制造DRAM存储单元和逻辑电路，该方法能够通过防止漏电流显影而提高DRAM存储单元的刷新特性，并使能 半导体器件的可靠性的提高，功耗降低，并且通过将集成电路组装成单个芯片，能够提高集成电路的性能和处理速度。 在形成用作栅电极的多晶硅层之后，形成氮化硅膜以覆盖DRAM存储单元的源极/漏极区域，并引起其它源极/漏极区域和多晶硅层的暴露。 通过自对准硅化物技术在半导体衬底上形成金属硅化物层。
-
公开(公告)号：US20060027883A1
公开(公告)日：2006-02-09
申请号：US11241921
申请日：2005-10-04
IPC分类号： H01L29/94
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure (2) formed in the main surface of a semiconductor substrate (1), a pair of extensions (3) and source/drain regions (4) selectively formed in the main surface of the semiconductor substrate (1) to face each other through a channel region (50), a silicon oxide film (5) formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) formed on sides of the silicon oxide film (5), a gate insulating film (7) formed on the main surface of the semiconductor substrate (1) in the part in which the channel region (50) is formed, and a gate electrode (8) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译： 本发明的目的是获得其中通道长度减小而不增加栅极电阻以实现更高的操作速度的半导体器件及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体的主表面中选择性地形成的一对延伸部（3）和源极/漏极区域（4） 衬底（1）通过沟道区域（50）彼此面对，通过硅氧化膜形成在沟槽型元件隔离结构（2）上和源极/漏极区域（4）上的氧化硅膜（5） （12），形成在氧化硅膜（5）的侧面上的侧壁（6），形成在半导体衬底（1）的主表面上的沟道区域（50）的部分中的栅极绝缘膜（7） 以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形状填充凹部的栅电极（8）。
-
3.发明授权Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer 失效半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟公开(公告)号：US06548871B1
公开(公告)日：2003-04-15
申请号：US09543349
申请日：2000-04-05
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/823475 , H01L23/522 , H01L23/535 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
摘要翻译： 属于彼此相邻的分离元件的两个源极/漏极区域（20）通过与形成栅电极的一部分的金属层（10）的高度相同的高度的金属层（14）连接。 在制造过程中，绝缘层（8）由除两个绝缘层（7）和（16）之外的其它材料制成。 两个绝缘层（7）和（16）作为用于将金属层（10），（14）和（15）埋入其中并由相同材料制成的模具。 因此，金属层（14）可以形成在与金属层（10）的高度相同的高度。 因此，通过布置在较短距离处的布线而连接的部分被连接，同时降低布线能力。
-
公开(公告)号：US06383884B1
公开(公告)日：2002-05-07
申请号：US09496057
申请日：2000-02-02
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28247 , H01L29/66537
摘要： A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.
摘要翻译： 半导体器件包括硅衬底（1），一对隔离绝缘膜（9），沟道区（2），一对源/漏区（3），一对氧化硅膜（4），形成在 硅衬底（1）的上表面覆盖在源极/漏极区（3）上，并且栅极结构（8）形成在由硅衬底（1）的上表面限定的第一凹部中，沟道 区域（2）和一对氧化硅膜（4）的侧表面。 栅极结构（8）包括形成在硅衬底（1）的上表面上的栅氧化膜（5），一对氧化硅膜（6），形成在该一对氧化硅的侧表面的下部 以及填充由氧化硅膜（4）的侧面的上部，氧化硅膜（6）和栅极氧化膜（5）所包围的第二凹部的金属膜（7）。 提供了一种制造半导体器件的方法，其在不降低驱动能力的情况下实现栅极长度的减小以实现操作速度的提高。
-
5.发明授权Semiconductor device including inversely tapered gate electrode and manufacturing method thereof 失效包括反锥形栅电极的半导体器件及其制造方法公开(公告)号：US06661066B2
公开(公告)日：2003-12-09
申请号：US09401849
申请日：1999-09-22
IPC分类号： H01L31119
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译： 一种半导体器件和制造方法，包括形成在半导体衬底（1）的主表面上的沟槽型元件隔离结构（2）的MOSFET。 在主表面中选择性地形成一对延伸部（3）和源极/漏极区域（4），以便通过沟道区域（50）彼此面对，在沟槽型（5）上形成氧化硅膜 元件隔离结构（2），并且通过氧化硅膜（12）在源极/漏极区域（4）上，在氧化硅膜（5）的侧面上形成侧壁（6），栅极绝缘膜（7）为 形成在形成有沟道区域（50）的部分的主表面上，并且形成栅电极（8）以填充由侧壁（6）的侧面和上表面形成的倒锥形状的凹部 的栅极绝缘膜（7）。
-
公开(公告)号：US06214695B1
公开(公告)日：2001-04-10
申请号：US09291043
申请日：1999-04-14
申请人： Yasuo Inoue , Yasuyoshi Itoh , Katsuyuki Horita
发明人： Yasuo Inoue , Yasuyoshi Itoh , Katsuyuki Horita
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An object is to obtain a method of manufacturing semiconductor devices having trench isolation structure which accomplishes simplification of manufacturing process without deterioration of polishing uniformity. After a silicon oxide film (5) is deposited an HDP-CVD method, a polysilicon film (6) is deposited to such a thickness that the polysilicon film (6) on upper regions of raised areas is removed and the polysilicon film (6) in recessed areas remains in a first CMP process and that the polysilicon film (6) serves as a mask in a later etching process. Subsequently, the first CMP process is performed and the etching process to the silicon oxide film (5) is performed by using the polysilicon film (6) after the first CMP process as a mask to remove the silicon oxide film (5) in the upper regions of the raised areas, and a second CMP process is further performed to planarize the semiconductor substrate (1).
摘要翻译： 本发明的目的是获得一种制造具有沟槽隔离结构的半导体器件的方法，其实现了制造工艺的简化，而不会降低抛光均匀性。 在通过HDP-CVD法沉积氧化硅膜（5）之后，沉积多晶硅膜（6），使得去除凸起区域的上部区域上的多晶硅膜（6），并将多晶硅膜（6） 在凹陷区域保留在第一CMP工艺中，并且多晶硅膜（6）在稍后的蚀刻工艺中用作掩模。 随后，执行第一CMP处理，并且在第一CMP处理之后通过使用多晶硅膜（6）作为掩模来执行对氧化硅膜（5）的蚀刻处理，以去除上部的氧化硅膜（5） 并且进一步执行第二CMP处理以使半导体衬底（1）平坦化。
-
7.发明授权Method of manufacturing thin film transistor array substrate and display device 有权制造薄膜晶体管阵列基板和显示装置的方法公开(公告)号：US07799621B2
公开(公告)日：2010-09-21
申请号：US12266064
申请日：2008-11-06
申请人： Yasuyoshi Itoh , Toshio Araki
发明人： Yasuyoshi Itoh , Toshio Araki
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.
摘要翻译： 根据本发明的制造薄膜晶体管阵列基板的方法包括：形成由第一导电膜制成的图案; 以所述顺序层叠栅极绝缘膜，半导体层和抗蚀剂; 在厚度方向上形成具有台阶结构的抗蚀剂图案; 通过使用抗蚀剂图案形成第一导电膜的暴露区域和半导体层的图案; 在所述第一导电膜的暴露区域中形成与所述第一导电膜接触的第二导电膜形成的图案; 以及形成由第三导电膜制成的图案。 第一导电膜形成栅电极，第二导电膜形成源电极和漏电极。 第三导电膜形成像素电极，第二导电膜涂覆有上层膜。
-
公开(公告)号：US07397063B2
公开(公告)日：2008-07-08
申请号：US10898360
申请日：2004-07-26
申请人： Yasuyoshi Itoh , Kaoru Motonami
发明人： Yasuyoshi Itoh , Kaoru Motonami
IPC分类号： H01L29/04
CPC分类号： H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , Y10S257/913
摘要： A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.
摘要翻译： 半导体器件包括用作具有绝缘表面的基板的玻璃基板和位于与该玻璃基板重叠的位置的硅层。 硅层包括无定形吸气区域。 优选地，硅层包括用作有源元件区域的主区域，并且除了主区域之外的硅层的剩余部分中优选包含吸杂区域。 优选地，硅层可以包括用作薄膜晶体管的有源区的部分。
-
公开(公告)号：US20070034871A1
公开(公告)日：2007-02-15
申请号：US11420956
申请日：2006-05-30
申请人： Yasuyoshi Itoh , Toru Takeguchi
发明人： Yasuyoshi Itoh , Toru Takeguchi
IPC分类号： H01L29/04
CPC分类号： H01L29/78675 , H01L27/1296 , H01L29/78666
摘要： An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.
摘要翻译： 在绝缘基板的主表面上形成岛状半导体层。 岛状半导体层的侧壁基本上垂直于绝缘基板。 沿半导体层的侧壁形成绝缘膜。 绝缘膜形成为包括倾斜面，并且具有从半导体层的侧壁测量的宽度随着与底部距离的增加而减小的截面形状。 由于包含绝缘膜，可以在半导体层上形成具有良好阶梯覆盖的栅极绝缘膜，以防止导致栅电极断开的可能性。 此外，其中形成沟道区的半导体层的一部分的厚度是均匀的，以获得稳定的晶体管特性。
-
10.发明授权公开(公告)号：US06867455B2
公开(公告)日：2005-03-15
申请号：US10600344
申请日：2003-06-23
申请人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
发明人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/26586 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/42368 , H01L29/513 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7923
摘要： A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.
摘要翻译： 一种能够将多位信息保持在一个存储单元中的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽。 然后，使介入沟槽的栅极绝缘膜的氮化硅膜中的源极侧部分和漏极侧部分作为能够保持电荷的第一和第二电荷保持部分起作用。 在第一电荷被捕获在漏极侧并且第二电荷被捕获在源极侧的情况下，沟槽中的栅电极的一部分用作屏蔽。 如果向栅电极施加固定电位，则第二电荷保持部不受第一电荷引起的电场的影响，从而不抑制第二电荷的捕获。
-
-
-
-
-
-
-
-
-
搜索结果
34 条记录 (耗时 0.029 秒)
