公开(公告)号：US08307022B2

公开(公告)日：2012-11-06

申请号：US12130567

申请日：2008-05-30

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/588 ,  H03K3/84

摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.

摘要翻译： 随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极 隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

公开(公告)号：US07392271B2

公开(公告)日：2008-06-24

申请号：US10919291

申请日：2004-08-17

申请人： Shinichi Yasuda ,  Shinobu Fujita

发明人： Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58

摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

公开(公告)号：US08553464B2

公开(公告)日：2013-10-08

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

发明人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

IPC分类号： G11C11/35

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20080244489A1

公开(公告)日：2008-10-02

申请号：US12047547

申请日：2008-03-13

申请人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068

摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.

摘要翻译： 一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据， 交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层 电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连 折叠互连的下层。

公开(公告)号：US20090157780A1

公开(公告)日：2009-06-18

申请号：US12122503

申请日：2008-05-16

申请人： Shinichi YASUDA ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58

摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

公开(公告)号：US07949984B2

公开(公告)日：2011-05-24

申请号：US12047547

申请日：2008-03-13

申请人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5068

摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.

摘要翻译： 一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据， 交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层 电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连 折叠互连的下层。

公开(公告)号：US20090327379A1

公开(公告)日：2009-12-31

申请号：US12130567

申请日：2008-05-30

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F7/58

CPC分类号： G06F7/588 ,  H03K3/84

摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.

摘要翻译： 随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极 隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

公开(公告)号：US07772035B2

公开(公告)日：2010-08-10

申请号：US11860102

申请日：2007-09-24

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/28 ,  H01L24/31 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01016 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias, forming a solid-electrolytic layer on an upper surface of the first semiconductor substrate, mounting the second semiconductor substrate on the solid-electrolytic layer such that a lower surface of the second semiconductor substrate comes into contact with the solid-electrolytic layer, and applying a voltage between the plurality of first through substrate vias and the plurality of second through substrate vias, to form in the solid-electrolytic layer a plurality of connection electrodes, which are respectively connecting the plurality of second through substrate vias adjacent to the plurality of first through substrate vias to the plurality of first through substrate vias.

摘要翻译： 半导体器件的制造方法包括：制备具有形成在其中的第一集成电路的第一半导体衬底，并且包括多个第一贯通衬底通孔;以及第二半导体衬底，其具有形成在其中的第二集成电路，并且包括多个第二穿透衬底 通孔，在所述第一半导体衬底的上表面上形成固体电解质层，将所述第二半导体衬底安装在所述固体电解质层上，使得所述第二半导体衬底的下表面与所述固体电解质层接触;以及 在所述多个第一至第二基板通孔和所述多个第二贯穿基板通孔之间施加电压，以在所述固体电解质层中形成多个连接电极，所述多个连接电极分别连接所述多个第二贯穿基板通孔 首先通过基底通孔到达普拉 首先通过衬底通孔。

公开(公告)号：US20100072614A1

公开(公告)日：2010-03-25

申请号：US12504272

申请日：2009-07-16

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H01L23/52 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer.

摘要翻译： 三维集成电路设计方法包括在XY平面上形成用于原始集成电路的临时布局区域，该平面在X方向上短并且在垂直于X方向的Y方向上长，将临时布局区域分成 2N（N是不小于2的整数）或更多个子区域，为每个连续的N个子区域配置一个块以准备多个块，并且通过交替地将每个块的每个块交替地折叠来形成N个层的布局 以一个子区域为单位的Y方向，选择性地将各块的kN（k为1以上的整数）子区域和（kN + 1）个子区域设置为最上层和最下层中的一个。

公开(公告)号：US20090309646A1

公开(公告)日：2009-12-17

申请号：US12391640

申请日：2009-02-24

申请人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

发明人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

IPC分类号： G06G7/12 ,  H01L27/088

CPC分类号： H01L29/1054 ,  G06F7/588 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/7843 ,  H03K3/84

摘要： A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.

摘要翻译： 随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。 第一绝缘膜具有陷阱捕获和释放电荷，并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。