公开(公告)号：US20130228852A1

公开(公告)日：2013-09-05

申请号：US13600373

申请日：2012-08-31

申请人： Soichiro KITAZAKI ,  Masaru KIDOH ,  Mitsuru SATO ,  Ryota KATSUMATA ,  Tadashi IGUCHI

发明人： Soichiro KITAZAKI ,  Masaru KIDOH ,  Mitsuru SATO ,  Ryota KATSUMATA ,  Tadashi IGUCHI

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

公开(公告)号：US20120068252A1

公开(公告)日：2012-03-22

申请号：US13043714

申请日：2011-03-09

申请人： Ryota KATSUMATA ,  Kazuyuki HIGASHI ,  Yoshiaki FUKUZUMI

发明人： Ryota KATSUMATA ,  Kazuyuki HIGASHI ,  Yoshiaki FUKUZUMI

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，多层体，半导体构件和电荷存储层。 多层体设置在基板上，多个绝缘膜和电极膜交替堆叠，并且包括彼此相对的第一阶梯和第二阶梯。 半导体构件设置在设置有第一阶梯和第二阶梯的区域之外的多层体中，并且半导体构件在绝缘膜和电极膜的堆叠方向上延伸。 电荷存储层设置在每个电极膜和半导体部件之间。 每个电极膜包括形成在第一阶梯中的第一台阶，形成在第二楼梯中的第二台阶和连接第一台阶和第二平台的桥接部分。

公开(公告)号：US20130119456A1

公开(公告)日：2013-05-16

申请号：US13422294

申请日：2012-03-16

申请人： Masaru KITO ,  Ryota KATSUMATA

发明人： Masaru KITO ,  Ryota KATSUMATA

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7926 ,  H01L27/1157 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor device includes: a substrate; a stacked body provided above the substrate, including a selector gate and an insulating layer provided on the selector gate; an insulating film provided on a sidewall of a hole formed by penetrating the stacked body in the stacking direction; a channel body and a semiconductor layer. The channel body is provided on a sidewall of the insulating film in the hole, that blocks the hole near an end of the insulating layer side in the selector gate, and that encloses a cavity below a part that blocks the hole. The semiconductor layer is formed of a same material as the channel body and is embedded continuously in the hole above the part where the channel body blocks the hole.

摘要翻译： 根据一个实施例，半导体器件包括：衬底; 设置在所述基板上方的堆叠体，包括设置在所述选择器门上的选择栅和绝缘层; 设置在沿层叠方向穿过层叠体而形成的孔的侧壁上的绝缘膜; 通道体和半导体层。 通道体设置在孔中的绝缘膜的侧壁上，其阻挡在选择栅中的绝缘层侧的端部附近的孔，并且在封闭孔的部分下方包围空腔。 半导体层由与沟道体相同的材料形成，并且被连续地嵌入在通道体阻挡孔的部分上方的孔中。

公开(公告)号：US20110316069A1

公开(公告)日：2011-12-29

申请号：US12886010

申请日：2010-09-20

申请人： Hiroyasu TANAKA ,  Ryota KATSUMATA

发明人： Hiroyasu TANAKA ,  Ryota KATSUMATA

IPC分类号： H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a non-memory unit. The memory unit includes a stacked structure including electrode films stacked in a first direction, and a interelectrode insulating film provided between the electrode films, a select gate electrode stacked with the stacked structure along the first direction, a semiconductor pillar piercing the stacked structure and the select gate electrode along the first direction and a pillar portion memory layer provided between the electrode films and the semiconductor pillar. The non-memory unit includes a dummy conductive film including a portion in a layer being identical to at least one of the electrode films, a dummy select gate electrode in a layer being identical to the select gate electrode, a first non-memory unit contact electrode electrically connected to the dummy conductive and a second non-memory unit contact electrode electrically connected to the dummy select gate.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和非存储器单元。 存储单元包括堆叠结构，其包括在第一方向上堆叠的电极膜，以及设置在电极膜之间的电极间绝缘膜，沿着第一方向堆叠层叠结构的选择栅电极，穿过层叠结构的半导体柱和 沿着第一方向选择栅电极和设置在电极膜和半导体柱之间的柱部存储层。 非存储单元包括虚拟导电膜，其包括与至少一个电极膜相同的层中的部分，与选择栅电极相同的层中的虚拟选择栅电极，第一非存储单元触点 电连接到虚拟导电体的电极和与虚拟选择栅极电连接的第二非存储单元接触电极。

公开(公告)号：US20120241844A1

公开(公告)日：2012-09-27

申请号：US13236833

申请日：2011-09-20

申请人： Tadashi IGUCHI ,  Ryota KATSUMATA

发明人： Tadashi IGUCHI ,  Ryota KATSUMATA

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L23/481 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：第一和第二堆叠体，第一和第二半导体柱，连接部分，存储膜和分隔绝缘层。 堆叠的栅极包括沿着第一轴线堆叠的电极膜和设置在电极膜之间的电极间绝缘膜。 在堆叠体中设置有通孔。 半导体柱被填充到通孔中。 连接部电连接半导体支柱。 存储膜设置在半导体柱和电极膜之间。 分隔绝缘层分隔第一和第二电极膜。 分隔绝缘层侧的第一通孔的侧面和分隔绝缘层侧的第二贯通孔的侧面具有与从第一层叠体到第二贯通孔的第二轴正交的平面的部分 第二堆叠体。

公开(公告)号：US20120241843A1

公开(公告)日：2012-09-27

申请号：US13236744

申请日：2011-09-20

申请人： Hiromitsu IINO ,  Ryota KATSUMATA

发明人： Hiromitsu IINO ,  Ryota KATSUMATA

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0688 ,  H01L21/76801 ,  H01L23/5329 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列部分，第一接触部分和外围电路部分。 第一接触部分与第一平面中的存储单元阵列部分并置。 外围电路部分与第一平面中的存储单元阵列部分并置。 存储单元阵列部分包括第一层叠体，第一半导体层和存储膜。 第一接触部分包括第一接触部分绝缘层和多个第一接触电极。 外围电路部分包括外围电路，结构体，外围电路部分绝缘层和外围电路部分接触电极。 沿着与周边电路部绝缘层的第一轴垂直的轴的宽度小于第一粒子的直径。