公开(公告)号：US08105904B2

公开(公告)日：2012-01-31

申请号：US12704233

申请日：2010-02-11

申请人： Yong-Chul Oh ,  Kang-Uk Kim

发明人： Yong-Chul Oh ,  Kang-Uk Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894

摘要： A semiconductor device includes an insulation layer disposed on a substrate having a first area and a second area, a first wiring disposed on the insulation layer in the first area, a first active structure disposed on the first wiring, a first gate insulation layer enclosing the first upper portion, a first gate electrode disposed on the first gate insulation layer, a first impurity region disposed at the first lower portion, and a second impurity region disposed at the first upper portion. The first wiring may extend in a first direction. The first active structure includes a first lower portion extending in the first direction and a first upper portion protruding from the first lower portion. The first gate electrode may extend in a second direction. The first impurity region may be electrically connected to the first wiring.

摘要翻译： 半导体器件包括设置在具有第一区域和第二区域的衬底上的绝缘层，设置在第一区域中的绝缘层上的第一布线，设置在第一布线上的第一有源结构，第一栅极绝缘层， 第一上部，设置在第一栅极绝缘层上的第一栅极电极，设置在第一下部的第一杂质区域和设置在第一上部的第二杂质区域。 第一布线可以沿第一方向延伸。 第一主动结构包括沿第一方向延伸的第一下部部分和从第一下部部分突出的第一上部部分。 第一栅电极可以在第二方向上延伸。 第一杂质区域可以电连接到第一布线。

公开(公告)号：US20100197121A1

公开(公告)日：2010-08-05

申请号：US12656440

申请日：2010-01-29

申请人： Kang-Uk Kim ,  Yong-Chul Oh

发明人： Kang-Uk Kim ,  Yong-Chul Oh

IPC分类号： H01L21/20

CPC分类号： H01L29/66666 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供衬底，所述衬底包括单晶硅并具有所述第一区域和第二区域; 在第一区域中从基板的顶表面生长柱; 形成包括第一栅极结构的垂直沟道晶体管，使得第一栅极结构围绕柱的中心部分; 以及在所述衬底的所述第二区域上形成第二晶体管，使得所述第二晶体管包括第二栅极结构。

公开(公告)号：US08884340B2

公开(公告)日：2014-11-11

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L21/336 ,  H01L29/772 ,  G11C11/404 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US08435855B2

公开(公告)日：2013-05-07

申请号：US12656440

申请日：2010-01-29

申请人： Kang-Uk Kim ,  Yong-Chul Oh

发明人： Kang-Uk Kim ,  Yong-Chul Oh

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7827

摘要： A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供衬底，所述衬底包括单晶硅并具有所述第一区域和第二区域; 在第一区域中从基板的顶表面生长柱; 形成包括第一栅极结构的垂直沟道晶体管，使得第一栅极结构围绕柱的中心部分; 以及在所述衬底的第二区域上形成第二晶体管，使得所述第二晶体管包括第二栅极结构。

公开(公告)号：US06670689B2

公开(公告)日：2003-12-30

申请号：US09990417

申请日：2001-11-21

申请人： Yong-Chul Oh ,  Jun-Yong Roh

发明人： Yong-Chul Oh ,  Jun-Yong Roh

IPC分类号： H01L2900

CPC分类号： H01L21/76229

摘要： A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.

摘要翻译： 具有浅沟槽隔离（STI）结构的半导体器件及其制造方法，其减小相邻P-FET之间的漏电流。 该器件包括具有第一和第二沟槽的半导体衬底，第一沟槽形成在电池区域中; 形成在所述第一沟槽和所述第二沟槽的内表面上的第一侧壁氧化物层; 形成在所述第二沟槽中的所述第一侧壁氧化物层的表面上的第二侧壁氧化物层; 形成在所述第一沟槽中的所述第一侧壁氧化物层上的第一浮雕衬垫; 形成在所述第一沟槽中的所述第一浮雕衬垫上并且还形成在所述第二沟槽中的所述第二侧壁氧化物层上的第二浮雕衬垫; 以及形成在第一和第二沟槽内的电介质材料。

公开(公告)号：US07833864B2

公开(公告)日：2010-11-16

申请号：US11738620

申请日：2007-04-23

申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

IPC分类号： H01L21/8234

CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

公开(公告)号：US07307008B2

公开(公告)日：2007-12-11

申请号：US10622915

申请日：2003-07-18

申请人： Yong-Chul Oh ,  Gyo-Young Jin

发明人： Yong-Chul Oh ,  Gyo-Young Jin

IPC分类号： H01L21/425

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.

摘要翻译： 在集成电路上形成单元焊盘接触孔的方法包括在集成电路基板上形成相邻栅极，该集成电路基板具有在栅极之间延伸的源极/漏极区域。 栅极间隔物形成在相邻栅极的相对侧壁上。 形成与栅极和栅极间隔物对准的电池垫接触孔，其暴露集成电路基板中的源极/漏极区域。 在电池垫接触孔中形成第一多晶膜。 通过离子注入第一多晶硅膜，在源极/漏极区域中形成离子区，而在第一多晶膜上形成基本上填充电池垫接触孔的第二多晶硅膜。

公开(公告)号：US08183613B2

公开(公告)日：2012-05-22

申请号：US12683179

申请日：2010-01-06

申请人： Hoon Jeong ,  Yong-Chul Oh ,  Sung-In Hong ,  Sung-Hwan Kim ,  Yong-Lack Choi ,  Ho-Ju Song

发明人： Hoon Jeong ,  Yong-Chul Oh ,  Sung-In Hong ,  Sung-Hwan Kim ,  Yong-Lack Choi ,  Ho-Ju Song

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.

摘要翻译： 存储器件包括绝缘层，有源图案，栅极绝缘层和栅电极。 绝缘层形成在基板上。 活性图案形成在绝缘层上，并且在突起之间包括两个突起和凹部。 有源图案分别在远离基板的突起的上部分别包括第一杂质区域和第二杂质区域，以及用作用于存储数据的浮体的其它部分的基极区域。 栅极绝缘层形成在活性图案的表面上。 栅电极形成在栅绝缘层上，并且围绕有源图案的下部并且部分地填充凹部。

公开(公告)号：US07223649B2

公开(公告)日：2007-05-29

申请号：US10922055

申请日：2004-08-18

申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

公开(公告)号：US06187651B1

公开(公告)日：2001-02-13

申请号：US09306496

申请日：1999-05-06

申请人： Yong-Chul Oh

发明人： Yong-Chul Oh

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate and lining the trench with a first electrically insulating layer. A stress-relief nitride layer is then formed on the first electrically insulating layer, opposite sidewalls of the trench. The trench is then filled with a second electrically insulating layer. The second electrically insulating layer is then planarized. This is followed by the steps of etching the stress-relief nitride layer and then forming a third electrically insulating layer on the planarized second electrically insulating layer and on the stress-relief nitride layer. The step of forming the trench is preferably preceded by the step of forming a patterned pad nitride layer on the semiconductor substrate. The pad nitride layer may be used as a mask when etching the substrate to define the trench. The step of planarizing the second electrically insulating layer may also comprise the step of planarizing the second electrically insulating layer using the patterned pad nitride layer as an etch stop.

摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在半导体衬底中形成沟槽并用第一电绝缘层衬套沟槽。 然后在沟槽的相对侧壁的第一电绝缘层上形成应力消除氮化物层。 然后用第二电绝缘层填充沟槽。 然后将第二电绝缘层平坦化。 之后是在平坦化的第二电绝缘层上和应力消除氮化物层上刻蚀应力消除氮化物层，然后形成第三电绝缘层的步骤。 形成沟槽的步骤优选地在半导体衬底上形成图案化衬垫氮化物层的步骤之前。 当蚀刻衬底以限定沟槽时，衬垫氮化物层可用作掩模。 平面化第二电绝缘层的步骤还可以包括使用图案化衬垫氮化物层作为蚀刻停止层来平坦化第二电绝缘层的步骤。