公开(公告)号：US20050156154A1

公开(公告)日：2005-07-21

申请号：US10707840

申请日：2004-01-16

申请人： Huilong Zhu ,  Bruce Doris ,  Dan Mocuta

发明人： Huilong Zhu ,  Bruce Doris ,  Dan Mocuta

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78654

摘要： Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

摘要翻译： 升高的Si / SiGe源极和漏极区域包括在SiGe侧壁上的外延生长的硅。 epi硅可防止Ge在硅化过程中的不利影响，包括Ge扩散和硅化物线断裂。 Si也增加了有效面积。

公开(公告)号：US20050098829A1

公开(公告)日：2005-05-12

申请号：US10701526

申请日：2003-11-06

申请人： Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/8238 ,  H01L27/01

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： A semiconductor device has selectively applied thin tensile films and thin compressive films, as well as thick tensile films and thick compressive films, to enhance electron and hole mobility in CMOS circuits. Fabrication entails steps of applying each film, and selectively removing each applied film from areas that would not experience performance benefit from the applied stressed film.

摘要翻译： 半导体器件已经选择性地施加薄的拉伸膜和薄的压缩膜，以及厚的拉伸膜和厚的压缩膜，以增强CMOS电路中的电子和空穴迁移率。 制造需要施加每个膜的步骤，并且从施加的应力膜不会经历性能的区域中选择性地去除每个所施加的膜。

公开(公告)号：US20070170507A1

公开(公告)日：2007-07-26

申请号：US11693377

申请日：2007-03-29

申请人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US20060172495A1

公开(公告)日：2006-08-03

申请号：US10905978

申请日：2005-01-28

申请人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Philip Oldiges ,  Meikel Ioeng ,  Min Yang ,  Huajie Chen

IPC分类号： H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US20060157706A1

公开(公告)日：2006-07-20

申请号：US11037622

申请日：2005-01-18

申请人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen ,  Patricia Mooney ,  Stephen Bedell

发明人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen ,  Patricia Mooney ,  Stephen Bedell

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

摘要翻译： 本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。 广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

公开(公告)号：US20060124974A1

公开(公告)日：2006-06-15

申请号：US10905101

申请日：2004-12-15

申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

IPC分类号： H01L29/80

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

公开(公告)号：US20080064197A1

公开(公告)日：2008-03-13

申请号：US11931387

申请日：2007-10-31

申请人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce Doris ,  Huajie Chen

IPC分类号： H01L21/3205

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

公开(公告)号：US20080048233A1

公开(公告)日：2008-02-28

申请号：US11835182

申请日：2007-08-07

申请人： Huilong Zhu ,  Bruce Doris

发明人： Huilong Zhu ,  Bruce Doris

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.

摘要翻译： 提供了一种使用薄SiGe层在半导体衬底上制造鳍结构以在硅衬底和硅片部分之间产生空隙的方法。 还提供了通过这种方法制造的翅片结构。

公开(公告)号：US20060237790A1

公开(公告)日：2006-10-26

申请号：US11473835

申请日：2006-06-23

申请人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce Doris ,  Meikei Ieong ,  Philip Oldiges ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

摘要翻译： 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

公开(公告)号：US20060180866A1

公开(公告)日：2006-08-17

申请号：US10906335

申请日：2005-02-15

申请人： Huilong Zhu ,  Bruce Doris

发明人： Huilong Zhu ,  Bruce Doris

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7842 ,  H01L29/7854 ,  H01L29/78645 ,  H01L2924/0002 ,  H01L2924/00

摘要： A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

摘要翻译： FINFET栅极的一部分由应力材料代替，以对FINFET的沟道施加应力，以增强电子和空穴的迁移率并提高性能。 FINFET具有SiGe / Si堆叠栅极，并且在硅化之前，选择性地蚀刻栅极的SiGe部分以形成栅极间隙，使得栅极足够薄以完全硅化。 在硅化之后，栅间隙填充有应力氮化物膜，以在沟道中产生应力并增强FINFET的性能。