公开(公告)号：US20070202639A1

公开(公告)日：2007-08-30

申请号：US11741441

申请日：2007-04-27

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20070122961A1

公开(公告)日：2007-05-31

申请号：US11560925

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US20070120197A1

公开(公告)日：2007-05-31

申请号：US11561047

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US20070111421A1

公开(公告)日：2007-05-17

申请号：US11618751

申请日：2006-12-30

申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

公开(公告)号：US20060027868A1

公开(公告)日：2006-02-09

申请号：US11244291

申请日：2005-10-06

申请人： Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L27/12

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

摘要翻译： 在衬底上形成的半导体结构和形成半导体的工艺。 半导体包括具有场效应晶体管（FETS）的第一部分和场效应晶体管的第二部分的多个场效应晶体管。 第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。 第二应力层具有第二厚度，并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。

公开(公告)号：US20060014338A1

公开(公告)日：2006-01-19

申请号：US10710272

申请日：2004-06-30

申请人： Bruce Doris ,  Diane Boyd ,  Huilong Zhu

发明人： Bruce Doris ,  Diane Boyd ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/7842

摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.

摘要翻译： 形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

公开(公告)号：US20050239242A1

公开(公告)日：2005-10-27

申请号：US10709248

申请日：2004-04-23

申请人： Huilong Zhu ,  Bruce Doris

发明人： Huilong Zhu ,  Bruce Doris

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present invention provides a device structure and method of forming a finFet device having stacked fins. The method of the present invention comprises: providing a substrate with a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; forming a first fin and a second fin in the second semiconductor layer; masking the first fin; and forming a third fin in the first semiconductor layer, where the second fin is stacked on the third fin. The structure of the present invention comprises: a semiconductor substrate having a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; a first and second fin formed in the second semiconductor layer; and a third fin formed in the first semiconductor layer, where the second fin is stacked on the third fin.

摘要翻译： 本发明提供一种形成具有堆叠翅片的鳍片装置的装置结构和方法。 本发明的方法包括：在第一绝缘体层上提供具有第一半导体层的衬底，在第一半导体层上提供第二绝缘体层，在第二绝缘体层上提供第二半导体层; 在所述第二半导体层中形成第一鳍片和第二鳍片; 掩蔽第一鳍; 以及在所述第一半导体层中形成第三鳍​​片，其中所述第二鳍片堆叠在所述第三鳍片上。 本发明的结构包括：具有在第一绝缘体层上的第一半导体层，第一半导体层上的第二绝缘体层和第二绝缘体层上的第二半导体层的半导体衬底; 形成在所述第二半导体层中的第一和第二鳍; 以及形成在第一半导体层中的第三鳍，​​其中第二鳍片堆叠在第三鳍片上。

公开(公告)号：US20050233565A1

公开(公告)日：2005-10-20

申请号：US10709129

申请日：2004-04-15

申请人： Huilong Zhu ,  Bruce Doris

发明人： Huilong Zhu ,  Bruce Doris

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.

摘要翻译： 提供了一种使用薄SiGe层在半导体衬底上制造鳍结构以在硅衬底和硅片部分之间产生空隙的方法。 还提供了通过这种方法制造的翅片结构。

公开(公告)号：US20050189589A1

公开(公告)日：2005-09-01

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20050093030A1

公开(公告)日：2005-05-05

申请号：US10695748

申请日：2003-10-30

申请人： Bruce Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。