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    STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION
    1.
    发明申请
    STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION 失效
    用于产生用于MOSFET通道移动性修改的局部机械栅极应力的结构和方法

    公开(公告)号：US20060124974A1

    公开(公告)日：2006-06-15

    申请号：US10905101

    申请日：2004-12-15

    申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

    发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

    摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

    摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

    STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION
    2.
    发明申请
    STRUCTURE AND METHOD TO GENERATE LOCAL MECHANICAL GATE STRESS FOR MOSFET CHANNEL MOBILITY MODIFICATION 有权
    用于产生用于MOSFET通道移动性修改的局部机械栅极应力的结构和方法

    公开(公告)号：US20070111421A1

    公开(公告)日：2007-05-17

    申请号：US11618751

    申请日：2006-12-30

    申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

    发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

    摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

    摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

    Ultra thin channel MOSFET
    4.
    发明申请
    Ultra thin channel MOSFET 有权
    超薄通道MOSFET

    公开(公告)号：US20050048752A1

    公开(公告)日：2005-03-03

    申请号：US10650229

    申请日：2003-08-28

    申请人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

    发明人： Bruce Doris ,  Thomas Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/3205

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/78612 ,  H01L29/78621

    摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

    摘要翻译： 描述了制造薄沟道硅绝缘体上结构的方法。 本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域 ，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

    Sectional field effect devices and method of fabrication
    6.
    发明申请
    Sectional field effect devices and method of fabrication 有权
    截面场效应器件及其制造方法

    公开(公告)号：US20060240607A1

    公开(公告)日：2006-10-26

    申请号：US11433806

    申请日：2006-05-13

    申请人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Jeong ,  Jakub Kedzierski

    发明人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Jeong ,  Jakub Kedzierski

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

    摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。

    Sectional field effect devices and method of fabrication
    7.
    发明申请
    Sectional field effect devices and method of fabrication 有权
    截面场效应器件及其制造方法

    公开(公告)号：US20050127362A1

    公开(公告)日：2005-06-16

    申请号：US10732322

    申请日：2003-12-10

    申请人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

    发明人： Ying Zhang ,  Bruce Doris ,  Thomas Kanarsky ,  Meikei Ieong ,  Jakub Kedzierski

    IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/336 ,  H01L21/338 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

    摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。

    Hybrid planar and FinFET CMOS devices
    8.
    发明申请
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US20050263831A1

    公开(公告)日：2005-12-01

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    发明人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L31/113

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    Ultra-thin Si channel CMOS with improved series resistance
    9.
    发明申请
    Ultra-thin Si channel CMOS with improved series resistance 有权
    超薄Si沟道CMOS，具有改善的串联电阻

    公开(公告)号：US20050127408A1

    公开(公告)日：2005-06-16

    申请号：US10735736

    申请日：2003-12-16

    申请人： Bruce Doris ,  Meikei Ieong ,  Thomas Kanarsky

    发明人： Bruce Doris ,  Meikei Ieong ,  Thomas Kanarsky

    IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

    CPC分类号： H01L27/1203 ,  H01L21/823814 ,  H01L21/84

    摘要： Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.

    摘要翻译： 薄硅沟道SOI器件具有更清晰的子阈值斜率，高迁移率和更好的短沟道效应控制的优点，但呈现增加串联电阻的典型缺点。 通过使用升高的源极 - 漏极（RSD）和使用在nFET和pFET之间去耦合的选择性外延Si生长来扩展CMOS对中的pFET晶体管上的源极漏极来避免该高串联电阻。 通过这样做，串联电阻得到改善，扩展在RSD形成后植入，因此不暴露于RSD工艺的高热预算，而pFET和nFET可以实现独立的有效偏移。