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    Vectored flip-flop
    31.
    发明授权
    Vectored flip-flop 有权

    公开(公告)号：US10862462B2

    公开(公告)日：2020-12-08

    申请号：US16670830

    申请日：2019-10-31

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Simeon Realov

    IPC: H03K3/037 ,  H03K19/00

    Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

    Aging tolerant register file
    35.
    发明授权
    Aging tolerant register file 有权

    公开(公告)号：US10049724B2

    公开(公告)日：2018-08-14

    申请号：US15176069

    申请日：2016-06-07

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Sri Harsha Choday

    IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14

    Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.

    COMMON N-WELL STATE RETENTION FLIP-FLOP
    38.
    发明申请
    COMMON N-WELL STATE RETENTION FLIP-FLOP 有权
    普通N-WELL状态保持FLIP-FLOP

    公开(公告)号：US20160261252A1

    公开(公告)日：2016-09-08

    申请号：US14635849

    申请日：2015-03-02

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

    IPC: H03K3/356 ,  H03K3/3562

    CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/35625

    Abstract: Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, with one or more of the plurality of PMOS devices powered by an always-on supply and one or more of the plurality of PMOS devices powered by a power-gated supply. Other embodiments may be described and claimed.

    Abstract translation: 实施例包括用于状态保持电子设备的装置，方法和系统。 在实施例中，电子设备可以包括状态保持触发器，其具有与公共N阱耦合的多个P型金属氧化物半导体（PMOS）器件，其中一个或多个PMOS器件由始终 并且由电源门控电源供电的多个PMOS器件中的一个或多个。 可以描述和要求保护其他实施例。

    ULTRA-LOW CLOCK POWER MULTI-BIT FLIP-FLOPS USING UNIDIRECTIONAL DEVICES
    39.
    发明申请
    ULTRA-LOW CLOCK POWER MULTI-BIT FLIP-FLOPS USING UNIDIRECTIONAL DEVICES 有权

    公开(公告)号：US20240429901A1

    公开(公告)日：2024-12-26

    申请号：US18340679

    申请日：2023-06-23

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Abhishek Anil Sharma ,  Ram K. Krishnamurthy

    IPC: H03K3/037 ,  H03K17/687

    Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.

    LOW CONTENTION CURRENT CIRCUITS
    40.
    发明公开
    LOW CONTENTION CURRENT CIRCUITS 审中-公开

    公开(公告)号：US20240356552A1

    公开(公告)日：2024-10-24

    申请号：US18305147

    申请日：2023-04-21

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

    IPC: H03K19/0185 ,  G06F3/06 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    CPC classification number: H03K19/018521 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

    Abstract: A disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.

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