公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

公开(公告)号：US20230413684A1

公开(公告)日：2023-12-21

申请号：US17843976

申请日：2022-06-18

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/10 ,  H01L27/228 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

公开(公告)号：US20230317729A1

公开(公告)日：2023-10-05

申请号：US17710584

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li ,  Ian Alexander Young ,  Julien Sebot ,  Punyashloka Debashis

IPC: H01L27/118 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11803 ,  H01L29/78391 ,  H01L29/66984

Abstract: In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

公开(公告)号：US20230086080A1

公开(公告)日：2023-03-23

申请号：US17482131

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  John J. Plombon ,  Hai Li ,  Kaan Oguz ,  Tanay A. Gosavi ,  Emily Walker

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: In one embodiment, an apparatus includes a magnet, a first structure, and a second structure. The first structure includes a first conductive trace and a magnetoelectric material. The first conductive trace is coupled to an input voltage terminal, and the magnetoelectric material is coupled to the first conductive trace and the magnet. The second structure includes a superlattice structure and a second conductive trace. The superlattice structure includes one or more topological insulator materials. Moreover, the superlattice structure is coupled to the magnet and the second conductive trace, and the second conductive trace is coupled to an output voltage terminal.