公开(公告)号：US09734880B1

公开(公告)日：2017-08-15

申请号：US15088419

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Sadique Ul Ameen Sheik ,  Muhammad M. Khellah

IPC: G11C11/00 ,  G11C11/16 ,  G06N5/02

CPC classification number: G11C11/161 ,  G06N3/049 ,  G06N3/0635 ,  G06N3/088 ,  G06N5/025 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/54 ,  G11C13/0002

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

公开(公告)号：US20160149579A1

公开(公告)日：2016-05-26

申请号：US14553934

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

公开(公告)号：US20210043251A1

公开(公告)日：2021-02-11

申请号：US17001432

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10755771B2

公开(公告)日：2020-08-25

申请号：US16226385

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10698432B2

公开(公告)日：2020-06-30

申请号：US13801777

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

IPC: G05F1/00 ,  G05F1/46 ,  H02M3/156 ,  G05F1/563

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

公开(公告)号：US10685688B2

公开(公告)日：2020-06-16

申请号：US16234065

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/419 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C15/04

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US10333379B2

公开(公告)日：2019-06-25

申请号：US15382076

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Suphachai Chai Sutanthavibul ,  Iqbal Rajwani ,  Anupama A Thaploo ,  Surya Sasi Kiran Tallapragada ,  Daivik H Bhatt ,  Lei Jiang ,  Stephen Kim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H02M1/08 ,  H03K17/0812 ,  H03K17/687 ,  H02M3/158 ,  H02M1/088 ,  H03K19/00 ,  H02M1/00 ,  H03K17/08

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

公开(公告)号：US10269419B2

公开(公告)日：2019-04-23

申请号：US15604519

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C7/12 ,  G11C11/419

Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.

公开(公告)号：US10199080B2

公开(公告)日：2019-02-05

申请号：US15485059

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/419

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US20180342289A1

公开(公告)日：2018-11-29

申请号：US15604519

申请日：2017-05-24

Applicant: Intel Corporation

Inventor： Jaydeep P. KULKARNI ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Described is an apparatus which comprises: a memory bit-cell; a local bit-line (LBL) coupled to the memory bit-cell via a read port device; a NAND gate circuitry coupled to the LBL; and a stack of keepers coupled to the LBL, wherein at least one transistor of the stack of keepers is controllable according to an output of the NAND gate circuitry, wherein the stack of keepers includes transistors with variable strength which are to be turned on overtime.