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公开(公告)号：US11283456B2
公开(公告)日：2022-03-22
申请号：US17059480
申请日：2019-08-05
Applicant: Intel Corporation
Inventor： Ofir Degani , Igal Kushnir , Elan Banin , Rotem Banin
Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.
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公开(公告)号：US20210391853A1
公开(公告)日：2021-12-16
申请号：US17255291
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Benjamin Jann , Ashoke Ravi , Satwik Patnaik , Elan Banin , Ofir Degani , Nebil Tanzi , Brandon Davis , Igal Kushnir , Jonathan Jensen , Sidharth Dalmia , Peter Pawliuk
Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.
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公开(公告)号：US11121731B2
公开(公告)日：2021-09-14
申请号：US16550574
申请日：2019-08-26
Applicant: Intel Corporation
Inventor： Ashoke Ravi , Benjamin Jann , Satwik Patnaik , Elan Banin , Igal Kushnir , Ofir Degani , Alexandros Margomenos
Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
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公开(公告)号：US11095427B1
公开(公告)日：2021-08-17
申请号：US17033059
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Rotem Banin , Elan Banin , Ofir Degani , Ronen Gernizky , Ashoke Ravi
Abstract: A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.
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公开(公告)号：US10788794B2
公开(公告)日：2020-09-29
申请号：US16564538
申请日：2019-09-09
Applicant: Intel Corporation
Inventor： Ofir Degani , Elan Banin , Eran Ben Ami
Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
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Patent Agency Ranking
36.发明申请公开(公告)号：US20200228122A1
公开(公告)日：2020-07-16
申请号：US16629170
申请日：2017-08-07
Applicant: Intel Corporation
Inventor： Ashoke Ravi , Ofir Degani
Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
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公开(公告)号：US10659061B2
公开(公告)日：2020-05-19
申请号：US16472835
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Elias Nassar , Eyal Fayneh , Inbar Falkov , Elan Banin , Rotem Banin , Ofir Degani , Samer Nassar
Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
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公开(公告)号：US20200004207A1
公开(公告)日：2020-01-02
申请号：US16564538
申请日：2019-09-09
Applicant: Intel Corporation
Inventor： Ofir Degani , Elan Banin , Eran Ben Ami
Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
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公开(公告)号：US20190334533A1
公开(公告)日：2019-10-31
申请号：US16472835
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Elias Nassar , Eyal Fayneh , Inbar Falkov , Elan Banin , Rotem Banin , Ofir Degani , Samer Nassar
Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
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公开(公告)号：US10459407B1
公开(公告)日：2019-10-29
申请号：US16023973
申请日：2018-06-29
Applicant: Intel Corporation
Inventor： Ofir Degani , Elan Banin , Eran Ben Ami
Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
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