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    ENABLING LATE-BINDING OF SECURITY FEATURES VIA CONFIGURATION SECURITY CONTROLLER FOR ACCELERATOR DEVICES
    33.
    发明申请
    ENABLING LATE-BINDING OF SECURITY FEATURES VIA CONFIGURATION SECURITY CONTROLLER FOR ACCELERATOR DEVICES 有权

    公开(公告)号：US20210150033A1

    公开(公告)日：2021-05-20

    申请号：US17129243

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Alpa Trivedi ,  Steffen Schulz ,  Patrick Koeberl

    IPC: G06F21/57 ,  G06F21/44 ,  G06F30/331 ,  G06F9/38

    Abstract: An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed. The apparatus includes a security controller to initialize as part of a secure boot and attestation chain of trust; receive configuration data for portions of the security controller, the portions comprising components of the security controller capable of re-programming; verify and validate the configuration data to as originating from a secure and trusted source; and responsive to successful verification and validation of the configuration data, re-program the portions of the security controller based on the configuration data.

    BROADCAST REMOTE SEALING FOR SCALABLE TRUSTED EXECUTION ENVIRONMENT PROVISIONING
    34.
    发明申请
    BROADCAST REMOTE SEALING FOR SCALABLE TRUSTED EXECUTION ENVIRONMENT PROVISIONING 有权

    公开(公告)号：US20210112073A1

    公开(公告)日：2021-04-15

    申请号：US17129223

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Steffen Schulz ,  Alpa Trivedi ,  Patrick Koeberl

    IPC: H04L29/06 ,  G06F21/76

    Abstract: An apparatus to facilitate broadcast remote sealing for scalable trusted execution environment provisioning is disclosed. The apparatus includes one or more processors to: request a group status report to confirm a status of a group of trusted execution platforms from a cloud service provider (CSP) providing scalable runtime validation for on-device design rule checks; validate, by a tenant, a minimum trusted computing base (TCB) declared with the group status report; determine, based on validation of the minimum TCB, whether a set of group members of the group of trusted execution platforms satisfies security requirements of the tenant; responsive to the set of group members satisfying the security requirement, utilize a group public key to encrypt a workload of the tenant; and send the encrypted workload to the CSP for storage by the CSP and subsequent execution by an execution platform of the group using a private group key.

    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
    35.
    发明申请
    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS 有权

    公开(公告)号：US20210110099A1

    公开(公告)日：2021-04-15

    申请号：US17132306

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

    IPC: G06F30/398

    Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

    Dynamic configuration and peripheral access in a processor
    37.
    发明授权
    Dynamic configuration and peripheral access in a processor 有权

    公开(公告)号：US10565132B2

    公开(公告)日：2020-02-18

    申请号：US15651886

    申请日：2017-07-17

    Applicant: Intel Corporation

    Inventor： Steffen Schulz ,  Patrick Koeberl

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F11/30 ,  G06F11/07

    Abstract: In various implementations, a system includes a memory, a processor, and an execution-aware memory protection unit (EA-MPU). The EA-MPU is configured to regulate memory access by the processor based at least on the identity of a subject executable that requests access, and on the address to which access is requested, and on permissions information that identifies which subject executables are to be granted access to each of several memory regions. In various implementations, the permissions information itself is stored among the several memory regions. Various configurations of the permissions information can be used to provide shared memory regions for communication among two or more stand-alone trusted software modules, to protect access to devices accessible through memory-mapped I/O (MMIO), to implement a flexible watchdog timer, to provide security for software updates, to provide dynamic root of trust measurement services, and/or to support an operating system.

    Post-processing mechanism for physically unclonable functions
    38.
    发明授权
    Post-processing mechanism for physically unclonable functions 有权

    公开(公告)号：US10129036B2

    公开(公告)日：2018-11-13

    申请号：US14490402

    申请日：2014-09-18

    Applicant: Intel Corporation

    Inventor： Jiangtao Li ,  Wei Wu ,  Patrick Koeberl

    IPC: G06F11/30 ,  H04L9/32 ,  H04L9/08

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a post-processing mechanism for physically unclonable functions. An integrated circuit includes a physically unclonable function (PUF) unit including an adaptive PUF logic. The adaptive PUF logic receives a PUF response having a plurality of bits. The adaptive PUF logic also determines whether a record exists for bit among the plurality of bits in the PUF response. The record includes a stored bit location and a stored bit value corresponding to the stored bit location. The adaptive PUF logic also overrides a bit value of the bit in the PUF response with the stored bit value when it is determined that the record exists for the bit in the PUF response. The bit value of the bit in the PUF response is different from the stored bit value.

    Execution-aware memory protection
    39.
    发明授权
    Execution-aware memory protection 有权

    公开(公告)号：US09697142B2

    公开(公告)日：2017-07-04

    申请号：US15192049

    申请日：2016-06-24

    Applicant: INTEL CORPORATION

    Inventor： Patrick Koeberl ,  Steffen Schulz

    IPC: G06F12/14 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F12/1441 ,  G06F9/3005 ,  G06F9/3802 ,  G06F9/3824

    Abstract: Execution-Aware Memory protection technologies are described. A processor includes a processor core and a memory protection unit (MPU). The MPU includes a memory protection table and memory protection logic. The memory protection table defines a first protection region in main memory, the first protection region including a first instruction region and a first data region. The memory protection logic determines a protection violation by a first instruction when 1) an instruction address, resulting from an instruction fetch operation corresponding to the first instruction, is not within the first instruction region or 2) a data address, resulting from an execute operation corresponding to the first instruction, is not within the first data region.

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