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    Multiple register memory access instructions, processors, methods, and systems
    31.
    发明授权
    Multiple register memory access instructions, processors, methods, and systems 有权

    公开(公告)号：US10141033B2

    公开(公告)日：2018-11-27

    申请号：US15855600

    申请日：2017-12-27

    Applicant: Intel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G06F9/30 ,  G11C7/10

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    Packed data element predication processors, methods, systems, and instructions
    32.
    发明授权
    Packed data element predication processors, methods, systems, and instructions 有权

    公开(公告)号：US09990202B2

    公开(公告)日：2018-06-05

    申请号：US13931739

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Bret L. Toll ,  Ronak Singhal ,  Buford M. Guy ,  Mishali Naik

    IPC: G06F9/30

    CPC classification number: G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

    Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

    Instruction and logic for a cache prefetcher and dataless fill buffer
    33.
    发明授权
    Instruction and logic for a cache prefetcher and dataless fill buffer 有权
    缓存预取器和无数据填充缓冲区的指令和逻辑

    公开(公告)号：US09558127B2

    公开(公告)日：2017-01-31

    申请号：US14481266

    申请日：2014-09-09

    Applicant: Intel Corporation

    Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

    IPC: G06F12/08

    CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

    Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

    Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

    Programmable Counters for Counting Floating-Point Operations in SIMD Processors
    34.
    发明申请
    Programmable Counters for Counting Floating-Point Operations in SIMD Processors 审中-公开
    用于计数SIMD处理器浮点运算的可编程计数器

    公开(公告)号：US20160026464A1

    公开(公告)日：2016-01-28

    申请号：US14811552

    申请日：2015-07-28

    Applicant: Intel Corporation

    Inventor： Laura A. Knauth ,  Matthew C. Merten ,  Ronak Singhal ,  Hugh M. Caffrey

    IPC: G06F9/30

    CPC classification number: G06F9/3013 ,  G06F9/30109 ,  G06F9/30112 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

    Abstract: A processor includes one or more execution units to execute instructions, each having one or more elements in different element sizes using one or more registers in different register sizes. The processor further includes a counter configured to count a number of instructions performing predetermined types of operations executed by the one or more execution units. The processor further includes one or more registers to allow an external component to configure the counter to count a number of instructions associated with a combination of a register size and a element size (register/element size) and to retrieve a counter value produced by the counter.

    Abstract translation: 处理器包括执行指令的一个或多个执行单元，每个执行单元具有使用不同寄存器大小的一个或多个寄存器的不同元件大小的一个或多个元件。 处理器还包括计数器，其被配置为对执行由一个或多个执行单元执行的预定类型的操作的多个指令进行计数。 处理器还包括一个或多个寄存器，以允许外部组件配置计数器以对与寄存器大小和元素大小（寄存器/元素大小）的组合相关联的多个指令进行计数，并且检索由 计数器。

    Multiple register memory access instructions, processors, methods, and systems
    36.
    发明授权
    Multiple register memory access instructions, processors, methods, and systems 有权

    公开(公告)号：US10170165B2

    公开(公告)日：2019-01-01

    申请号：US15855626

    申请日：2017-12-27

    Applicant: Intel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G06F9/30 ,  G11C7/10

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

    Multiple register memory access instructions, processors, methods, and systems
    38.
    发明授权
    Multiple register memory access instructions, processors, methods, and systems 有权

    公开(公告)号：US10102888B2

    公开(公告)日：2018-10-16

    申请号：US15728293

    申请日：2017-10-09

    Applicant: Intel Corporation

    Inventor： Glenn Hinton ,  Bret Toll ,  Ronak Singhal

    IPC: G06F7/00 ,  G11C7/10 ,  G06F9/30

    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

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