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公开(公告)号：US20250087392A1
公开(公告)日：2025-03-13
申请号：US18367553
申请日：2023-09-13
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Shravana Kumar Katakam , Chih-Chao Yang
Abstract: A semiconductor device includes a first metallization level comprising a first electrode and a second metallization level comprising a second electrode. A resistor structure is disposed between the first electrode and the second electrode. The resistor structure comprises a first resistor element comprising a first side and a second side, wherein the first side has a larger area than an area of the second side, and a second resistor element stacked on the first resistor element, wherein the second resistor element contacts the second side of the first resistor element.
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公开(公告)号：US12207561B2
公开(公告)日：2025-01-21
申请号：US18061491
申请日：2022-12-05
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Shravana Kumar Katakam , Ashim Dutta , Chih-Chao Yang
Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.
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公开(公告)号：US11955152B2
公开(公告)日：2024-04-09
申请号：US17541401
申请日：2021-12-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ashim Dutta , Chih-Chao Yang , Theodorus E. Standaert , Daniel Charles Edelstein
Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.
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公开(公告)号：US11937435B2
公开(公告)日：2024-03-19
申请号：US17513273
申请日：2021-10-28
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Chih-Chao Yang
Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.
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公开(公告)号：US11778929B2
公开(公告)日：2023-10-03
申请号：US16286995
申请日：2019-02-27
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Ekmini Anuja De Silva , Jennifer Church
CPC classification number: H10N70/011 , H10B61/00 , H10B63/80 , H10N50/01 , H10N50/80 , H10N70/231 , H10N70/826 , H10N70/841
Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.
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Patent Agency Ranking
公开(公告)号：US11744083B2
公开(公告)日：2023-08-29
申请号：US16382519
申请日：2019-04-12
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Ekmini Anuja De Silva , Chih-Chao Yang
CPC classification number: H10B61/00 , H01L23/53209 , H10N50/01 , H10N50/10 , H10N50/80
Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.
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公开(公告)号：US20230178129A1
公开(公告)日：2023-06-08
申请号：US17541401
申请日：2021-12-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ashim Dutta , Chih-Chao Yang , Theodorus E. Standaert , Daniel Charles Edelstein
CPC classification number: G11C11/161 , H01L43/08 , H01L43/10 , H01L43/12 , H01L43/02 , H01L27/222
Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.
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38.发明公开公开(公告)号：US20230165156A1
公开(公告)日：2023-05-25
申请号：US17534485
申请日：2021-11-24
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Shyng-Tsong Chen , Terry A. Spooner , Chih-Chao Yang
IPC: H01L43/12 , H01L43/10 , H01L43/02 , H01L43/08 , G11C11/16 , H01L27/22 , H01L21/768 , H01L23/522
CPC classification number: H01L43/12 , H01L43/10 , H01L43/02 , H01L43/08 , G11C11/161 , H01L27/222 , H01L21/76885 , H01L23/5226
Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.
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公开(公告)号：US11621294B2
公开(公告)日：2023-04-04
申请号：US16886830
申请日：2020-05-29
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Saumya Sharma , Tianji Zhou , Chih-Chao Yang
Abstract: A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.
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公开(公告)号：US20230102165A1
公开(公告)日：2023-03-30
申请号：US17484453
申请日：2021-09-24
Applicant: International Business Machines Corporation
Inventor： Ashim Dutta , Chih-Chao Yang
Abstract: A semiconductor structure comprises a memory device comprising a first electrode, at least one memory element layer disposed on the first electrode, and a second electrode disposed on the at least one memory element layer. An encapsulation layer is disposed around side surfaces of the memory device. The semiconductor structure also comprises a conductive cap layer disposed on a top surface of the encapsulation layer and around a portion of side surfaces of the encapsulation layer. A contact is disposed on the second electrode and extends around the side surfaces of the memory device.
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