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公开(公告)号：US10720453B2
公开(公告)日：2020-07-21
申请号：US16394472
申请日：2019-04-25
IPC分类号： H01L29/66 , H01L27/12 , H03K17/567 , H03K17/70 , H01L21/285 , H01L29/40 , H01L29/45 , H01L23/522 , H01L23/532 , H01L21/84 , H01L29/808 , H01L29/04 , H01L29/08 , H01L29/16 , H01L29/735 , G06N3/04 , H01L27/06 , H01L29/417 , H01L21/8248 , H01L29/10 , G06N3/063 , H01L21/3213 , H01L29/737 , H01L29/80
摘要： A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
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公开(公告)号：US20200185516A1
公开(公告)日：2020-06-11
申请号：US16794473
申请日：2020-02-19
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L21/28 , H01L21/311
摘要： A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
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公开(公告)号：US20200103371A1
公开(公告)日：2020-04-02
申请号：US16148590
申请日：2018-10-01
IPC分类号： G01N27/414 , H03K19/0185 , H04W4/80 , G08C17/02 , G06K7/10 , G06K19/077
摘要： A wireless sensor circuit and sensor tag in which the output is directly converted to a frequency response. The sensor circuit includes a buffer transistor having gate, source and drain terminals configured as a source-follower, a gate resistor connected to the gate terminal of the buffer transistor, a supply voltage connected to the drain terminal of the buffer transistor, and an active load element and a capacitive load element connected to the source terminal of the buffer transistor. An input signal having an input frequency is applied to the buffer transistor via the gate resistor and an output signal is generated at the source terminal of the buffer transistor. The output frequency represents a response of the sensor circuit.
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公开(公告)号：US10553708B2
公开(公告)日：2020-02-04
申请号：US15689522
申请日：2017-08-29
IPC分类号： H01L29/66 , H01L29/423 , H01L29/786 , H01L27/108
摘要： A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
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公开(公告)号：US20200035691A1
公开(公告)日：2020-01-30
申请号：US16590199
申请日：2019-10-01
IPC分类号： H01L27/112 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/265
摘要： VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.
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公开(公告)号：US10476016B2
公开(公告)日：2019-11-12
申请号：US16138934
申请日：2018-09-21
IPC分类号： H01L21/28 , G06N3/063 , H01L51/00 , G11C11/54 , H01L29/08 , H01L51/05 , H01L21/8238 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/778 , H01L29/12 , H01L29/10 , H01L29/06 , H01L29/43 , H01L29/51 , H01L29/423 , H01L29/788
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
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公开(公告)号：US20190341382A1
公开(公告)日：2019-11-07
申请号：US16512522
申请日：2019-07-16
IPC分类号： H01L27/092 , H01L29/08 , H01L29/06 , H01L27/098 , H01L27/112 , H01L29/10 , H01L29/808 , H01L29/66 , H01L29/786 , H01L29/423 , H01L27/06
摘要： A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
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公开(公告)号：US10396103B2
公开(公告)日：2019-08-27
申请号：US15830639
申请日：2017-12-04
IPC分类号： H01L29/66 , H01L27/12 , H03K17/567 , H03K17/70 , H01L21/285 , H01L29/40 , H01L23/522 , H01L23/532 , H01L21/84 , H01L29/808 , H01L29/45 , H01L21/3213 , G06N3/063 , H01L29/737 , H01L29/80
摘要： A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
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公开(公告)号：US10387694B2
公开(公告)日：2019-08-20
申请号：US15487187
申请日：2017-04-13
发明人： Ali Afzali-Ardakani , Homa Alemzadeh , Maryam Ashoori , Bahman Hekmatshoartabari , Elham Khabiri
IPC分类号： G06F11/30 , G06K7/10 , H01L23/29 , H01L21/56 , G01D18/00 , G06N20/00 , H01L23/31 , H01L21/683 , G01D21/00 , G06N3/04
摘要： Systems, methods, and electronic circuits facilitating embedded sensor chips in polymer-based coatings are provided. In one example, a method comprises fabricating an electronic circuit, the electronic circuit comprising one or more semiconductor devices, one or more sensors, and a communication element; encapsulating the electronic circuit within an insulator, resulting in an encapsulated circuit; and dispersing the encapsulated circuit into a lacquer solution comprising a polymer carrier and a solvent.
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公开(公告)号：US20190252419A1
公开(公告)日：2019-08-15
申请号：US16394472
申请日：2019-04-25
IPC分类号： H01L27/12 , H01L29/66 , H01L29/808 , H01L21/285 , H01L29/40 , H01L23/532 , H03K17/567 , H01L23/522 , H01L21/84 , H03K17/70
摘要： A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
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