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公开(公告)号：US11270768B2
公开(公告)日：2022-03-08
申请号：US16808693
申请日：2020-03-04
发明人： Zheng Xu , Kangguo Cheng , Dexin Kong , Juntao Li
IPC分类号： G11C16/04 , G11C13/00 , H01L23/528 , H01L23/525 , H01L23/62
摘要： A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential.
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公开(公告)号：US11183636B2
公开(公告)日：2021-11-23
申请号：US16848603
申请日：2020-04-14
发明人： Kangguo Cheng , Juntao Li , Dexin Kong , Takashi Ando
摘要： Techniques for forming RRAM cells with increased density are provided. In one aspect, a method of forming a RRAM device includes: providing an underlayer disposed on a substrate; patterning trenches in the underlayer; forming bottom electrodes at two different levels of the underlayer that includes first bottom electrodes at bottoms of the trenches and second bottom electrodes along a top surface of the underlayer in between the trenches; depositing an insulating layer on the first/second bottom electrodes; and forming top electrodes on the insulating layer, wherein the top electrodes include word lines, wherein the first and second bottom electrodes include bit lines that are orthogonal to the word lines. A RRAM device is also provided.
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公开(公告)号：US11075200B2
公开(公告)日：2021-07-27
申请号：US16691732
申请日：2019-11-22
发明人： Zhenxing Bi , Kangguo Cheng , Zheng Xu , Dexin Kong
IPC分类号： H01L27/092 , H01L29/20 , H01L29/78 , H01L29/10 , H01L21/8238 , H01L21/033 , H01L29/08 , H01L29/66 , H01L21/8234 , H01L29/04 , H01L27/24
摘要： An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.
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公开(公告)号：US20200381621A1
公开(公告)日：2020-12-03
申请号：US16831379
申请日：2020-03-26
发明人： Juntao Li , Dexin Kong , Kangguo Cheng , Takashi Ando
IPC分类号： H01L45/00
摘要： A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.
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公开(公告)号：US10658583B1
公开(公告)日：2020-05-19
申请号：US16424981
申请日：2019-05-29
发明人： Juntao Li , Dexin Kong , Kangguo Cheng , Takashi Ando
IPC分类号： H01L45/00
摘要： A memory device with crossbar array structure includes two sets of parallel bottom electrodes positioned on a substrate. The lower bottom electrodes are located at a lower position relative to higher bottom electrodes. The device includes a first set of corner tips of the lower bottom electrodes, and a second set of corner tips at a top of the higher bottom electrodes. The device also includes a set of parallel top electrodes intersecting the two sets of parallel bottom electrodes. A dielectric is formed as a resistive random-access memory (RRAM) cell under each intersection of each top electrode and each of bottom electrode. The device further includes one set of contacts at one end of an array that contacts the lower bottom electrodes and another set of contacts at the other end of the array that contacts the higher bottom electrodes.
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公开(公告)号：US20200066797A1
公开(公告)日：2020-02-27
申请号：US16665527
申请日：2019-10-28
发明人： Dexin Kong , Takashi Ando , Kangguo Cheng , Juntao Li
摘要： A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.
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公开(公告)号：US20200064275A1
公开(公告)日：2020-02-27
申请号：US16110048
申请日：2018-08-23
摘要： A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.
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公开(公告)号：US20200052037A1
公开(公告)日：2020-02-13
申请号：US16058374
申请日：2018-08-08
发明人： Dexin Kong , Takashi Ando , Kangguo Cheng , Juntao Li
摘要： A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.
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公开(公告)号：US20200020540A1
公开(公告)日：2020-01-16
申请号：US16032750
申请日：2018-07-11
发明人： Kangguo Cheng , Zhenxing Bi , Juntao Li , Dexin Kong
IPC分类号： H01L21/308 , H01L29/66 , H01L21/033 , H01L21/8238
摘要： Techniques for tight pitch patterning of fins using a cyclic selective deposition process are provided. In one aspect, a method of patterning fins in a wafer includes: forming at least one mandrel on the wafer; forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel; removing the at least one mandrel; removing either the first dielectric or the second dielectric; and patterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks. A finFET device and method for forming a finFET device are also provided.
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公开(公告)号：US20200013896A1
公开(公告)日：2020-01-09
申请号：US16026880
申请日：2018-07-03
发明人： Zheng Xu , Zhenxing Bi , Dexin Kong , Qianwen Chen
IPC分类号： H01L29/788 , H01L27/11521 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/28 , H01L29/66
摘要： A method for fabricating a semiconductor device including a gate-all-around based non-volatile memory device includes forming gate-all-around field effect transistor (GAA FET) channels, depositing tunnel dielectric material around the GAA FET channels to isolate the GAA FET channels, forming a floating gate, including depositing first gate material over the isolated GAA FET channels, and forming at least one control gate, including depositing second gate material over the isolated GAA FET channels.
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