公开(公告)号：US12188961B2

公开(公告)日：2025-01-07

申请号：US17876652

申请日：2022-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kushagra Sinha ,  Zheng Xu ,  Yufei Wu ,  Myra Ahmad ,  Nikhilesh C Sahani

IPC: G01R1/067 ,  G01R31/28

Abstract: A testing apparatus and a method for testing an integrated circuit are described. One embodiment of the testing apparatus may comprise a main probe pin configured for electrical testing of a sample, the sample having a terminal pad, and a secondary probe pin configured for contact testing of the main probe pin against the terminal pad. In some embodiments, the testing apparatus may further comprise an indicator circuit electrically connected to the main probe pin and the secondary probe pin. The indicator circuit may output a signal when the main probe pin and the secondary probe pin are in simultaneous electrical engagement with the terminal pad.

公开(公告)号：US11877524B2

公开(公告)日：2024-01-16

申请号：US17469203

申请日：2021-09-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Dexin Kong ,  Zheng Xu

IPC: H10N70/00

CPC classification number: H10N70/063 ,  H10N70/826 ,  H10N70/8833 ,  H10N70/021

Abstract: Methods of forming a settable resistance device, settable resistance devices, and neuromorphic computing devices include isotropically etching a stack of layers, the stack of layers having an insulator layer in contact with a conductor layer, to selectively form divots in exposed sidewalls of the conductor layer. The stack of layers is isotropically etched to selectively form divots in exposed sidewalls of the insulator layer, thereby forming a tip at an interface between the insulator layer and the conductor layer. A dielectric layer is formed over the stack of layers to cover the tip. An electrode is formed over the dielectric layer, such that the dielectric layer is between the electrode and the tip.

公开(公告)号：US20230144050A1

公开(公告)日：2023-05-11

申请号：US17519924

申请日：2021-11-05

Applicant: International Business Machines Corporation

Inventor： Dexin Kong ,  Kangguo Cheng ,  Juntao Li ,  Zheng Xu

IPC: H01L45/00

CPC classification number: H01L45/1691 ,  H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144

Abstract: Semiconductor devices and methods for forming the semiconductor devices are described. An example semiconductor structure can include a substrate including a first electrode. The example semiconductor structure can further include a heater element directly contacting the first electrode in the substrate. The example semiconductor structure a phase change cell directly on the heater element. The sidewalls of the phase change cell can be encapsulated with a spacer. The example semiconductor structure a second electrode directly on the phase change cell and the spacer.

公开(公告)号：US20220181154A1

公开(公告)日：2022-06-09

申请号：US17677469

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Rasit Onur Topaloglu ,  Kafai Lai ,  Dongbing Shao ,  Zheng Xu

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

公开(公告)号：US11058337B2

公开(公告)日：2021-07-13

申请号：US15424265

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qianwen Chen ,  Huan Hu ,  Zheng Xu ,  Xin Zhang

IPC: A61B5/25 ,  A61B5/00 ,  B82Y40/00 ,  A61B5/291 ,  A61B5/296 ,  A61B5/398

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

公开(公告)号：US10930734B2

公开(公告)日：2021-02-23

申请号：US16174603

申请日：2018-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L21/02

Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.

公开(公告)号：US10915690B2

公开(公告)日：2021-02-09

申请号：US16383326

申请日：2019-04-12

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Yongan Xu ,  Shyng-Tsong Chen ,  Zheng Xu

IPC: G06F30/30 ,  G06F30/398

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

公开(公告)号：US10804274B2

公开(公告)日：2020-10-13

申请号：US16286843

申请日：2019-02-27

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Zheng Xu ,  Dexin Kong ,  Kangguo Cheng

IPC: H01L21/44 ,  H01L27/105 ,  H01L21/8229 ,  H01L29/06

Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.

公开(公告)号：US10790271B2

公开(公告)日：2020-09-29

申请号：US15954819

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： Zheng Xu ,  Chen Zhang ,  Ruqiang Bao ,  Dongbing Shao

IPC: H01L21/84 ,  H01L25/00 ,  H01L21/762 ,  H01L25/07 ,  H01L23/00 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.

公开(公告)号：US10608121B2

公开(公告)日：2020-03-31

申请号：US15846445

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L29/788 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.