公开(公告)号：US10762271B2

公开(公告)日：2020-09-01

申请号：US16145993

申请日：2018-09-28

Applicant: International Business Machines Corporation

Inventor： Myung-Chul Kim ,  Gi-Joon Nam ,  Shyam Ramji ,  Benjamin N. Trombley ,  Paul G. Villarrubia

IPC: G06F30/00 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A system and method of performing model-based refinement of a placement of components in integrated circuit generation select one of the components as a candidate component and postulate a move of the candidate component from an original position to a new position. The method includes defining nets associated with the candidate component. An initial perimeter and a new perimeter associated with each of the one or more nets are defined. The initial perimeter includes the candidate component at its original position and the new perimeter includes the candidate component at its new position. The method includes quantifying a change from the initial perimeter and the new perimeter and the original position and the new position, and obtaining a model of wires interconnecting the candidate component to the components of each of the nets. A result of the placement is provided for manufacture of the integrated circuit.

公开(公告)号：US10679120B2

公开(公告)日：2020-06-09

申请号：US14537826

申请日：2014-11-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

IPC: G06N3/06 ,  G06N3/04 ,  G06F30/327 ,  G06N3/063 ,  G06F119/06

Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

公开(公告)号：US20200074045A1

公开(公告)日：2020-03-05

申请号：US16679451

申请日：2019-11-11

Applicant: International Business Machines Corporation

Inventor： Woohyun Chung ,  Gi-Joon Nam ,  Lakshmi N. Reddy

IPC: G06F17/50 ,  G06F16/27 ,  G06F9/44

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

公开(公告)号：US10558775B2

公开(公告)日：2020-02-11

申请号：US15848556

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Myung-Chul Kim ,  Arjen Alexander Mets ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Alexander J. Suess ,  Benjamin Trombley ,  Paul G. Villarrubia

IPC: G06F17/50

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

公开(公告)号：US10534891B2

公开(公告)日：2020-01-14

申请号：US15842179

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Woohyun Chung ,  Gi-Joon Nam ,  Lakshmi N. Reddy

IPC: G06F17/50 ,  G06F9/44 ,  G06F16/27

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

公开(公告)号：US20190065657A1

公开(公告)日：2019-02-28

申请号：US15842179

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Woohyun Chung ,  Gi-Joon Nam ,  Lakshmi N. Reddy

IPC: G06F17/50 ,  G06F9/44 ,  G06F17/30

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

公开(公告)号：US10102061B2

公开(公告)日：2018-10-16

申请号：US15176714

申请日：2016-06-08

Applicant: International Business Machines Corporation

Inventor： Shawn P. Authement ,  Jente B. Kuang ,  Gi-Joon Nam

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G06F11/07 ,  G11C29/04

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

公开(公告)号：US20180121575A1

公开(公告)日：2018-05-03

申请号：US15341814

申请日：2016-11-02

Applicant: International Business Machines Corporation

Inventor： Jinwook Jung ,  Frank Musante ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi Reddy ,  Gustavo Tellez ,  Cindy S. Washburn

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G06F2217/06 ,  G06F2217/84

Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

公开(公告)号：US20150334022A1

公开(公告)日：2015-11-19

申请号：US14502505

申请日：2014-09-30

Applicant: International Business Machines Corporation

Inventor： Gi-Joon Nam ,  Sven Peyer ,  Ronald D. Rose ,  Sourav Saha

IPC: H04L12/801 ,  H04L12/46 ,  H04L12/751 ,  H04B3/32

CPC classification number: G06F17/5077 ,  G06F2217/08 ,  G06F2217/82 ,  G06F2217/84 ,  H04B3/32 ,  H04L12/4641 ,  H04L45/02 ,  H04L47/12

Abstract: A method and system to route connections of sub-networks in a design block of an integrated circuit and a computer program product are described. The system includes a memory device to store instructions to route the connections of the sub-networks, and a processor to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting. The MTL indicates a maximum length of each segment of each connection, each segment includes a different wirecode than an adjacent segment, and the wirecode defines a width, metal layer, and spacing for the segment.

Abstract translation: 描述了在集成电路的设计块和计算机程序产品中路由子网络的连接的方法和系统。 该系统包括存储设备以存储用于路由子网络的连接的指令，以及处理器，用于执行指令以确定每个子网络的每个连接的基线路由，识别噪声关键子网络 在基于拥塞的集成电路设计中，设置平均阈值长度（MTL），根据MTL对噪声关键子网络的连接进行分段，并根据分段重新路由基线路由。 MTL指示每个连接的每个段的最大长度，每个段包括与相邻段不同的有效线，并且该线码定义了段的宽度，金属层和间隔。

公开(公告)号：US20150254129A1

公开(公告)日：2015-09-10

申请号：US14197707

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Shawn P. Authement ,  Jente B. Kuang ,  Gi-Joon Nam

IPC: G06F11/10 ,  G11C29/52 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1048 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

Abstract translation: 在非AND（NAND）闪速存储器件中提供用于提供混合误差校正管理的机制。 耦合到NAND闪存模块的NAND快闪存储器模块和节点控制器与与节点控制器相关联的硬件逻辑实现的纠错码（ECC）引擎一起提供。 节点控制器被配置为确定错误计数是否小于或等于第一阈值数量的错误位，并且响应于错误计数小于或等于第一阈值数目的错误位，执行校正 通过硬件逻辑实现与节点控制器相关联的ECC引擎的错误位。 节点控制器还被配置为响应于错误计数大于第一阈值数量的错误位，将未校正的数据转发到软件逻辑实现的ECC引擎。