公开(公告)号：US20230054701A1

公开(公告)日：2023-02-23

申请号：US17406351

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  JUNTAO LI ,  Carl Radens

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

公开(公告)号：US20210118721A1

公开(公告)日：2021-04-22

申请号：US17131904

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  CHANRO PARK ,  JUNTAO LI ,  Ruilong Xie

IPC: H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/764 ,  H01L21/762

Abstract: Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.

公开(公告)号：US20200118891A1

公开(公告)日：2020-04-16

申请号：US16156391

申请日：2018-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  JUNTAO LI ,  ZHENXING BI

IPC: H01L21/84 ,  H01L27/12

Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.

公开(公告)号：US20200098860A1

公开(公告)日：2020-03-26

申请号：US16680633

申请日：2019-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  CHOONGHYUN LEE ,  JUNTAO LI ,  PENG XU

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

公开(公告)号：US20200058759A1

公开(公告)日：2020-02-20

申请号：US16662446

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  CHOONGHYUN LEE ,  JUNTAO LI ,  HENG WU ,  Peng Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

公开(公告)号：US20190393269A1

公开(公告)日：2019-12-26

申请号：US16018384

申请日：2018-06-26

Applicant: International Business Machines Corporation

Inventor： JUNTAO LI ,  Kangguo Cheng ,  TAKASHI ANDO ,  DEXIN KONG

IPC: H01L27/24 ,  H01L45/00

Abstract: Embodiments of the invention provide a semiconductor memory device. In some embodiments, the device includes a bottom electrode extending in a y-direction relative to top surface of a substrate and a top electrode extending in an x-direction relative to the top surface of the substrate. An active area is located at the cross-section between the bottom electrode and the top electrode and is located on vertical side walls extending in a z-direction of the semiconductor memory device with respect to the top surface of the substrate. An insulating layer is located in the active area in between the top electrode and the bottom electrode.

公开(公告)号：US20190334011A1

公开(公告)日：2019-10-31

申请号：US15965264

申请日：2018-04-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  CHOONGHYUN LEE ,  JUNTAO LI ,  HENG WU ,  Peng Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.