公开(公告)号：US11942396B2

公开(公告)日：2024-03-26

申请号：US17564219

申请日：2021-12-29

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Shu-Jung Yang ,  Yu-Min Lin ,  Chih-Yao Wang ,  Yu-Lin Chao

IPC: H01L23/427 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/427 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16235

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.

公开(公告)号：US11854961B2

公开(公告)日：2023-12-26

申请号：US17095744

申请日：2020-11-12

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/498 ,  H01L25/04 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/04 ,  H01L2924/0002

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

公开(公告)号：US20230170279A1

公开(公告)日：2023-06-01

申请号：US17564219

申请日：2021-12-29

Applicant: Industrial Technology Research Institute

Inventor： Heng-Chieh Chien ,  Shu-Jung Yang ,  Yu-Min Lin ,  Chih-Yao Wang ,  Yu-Lin Chao

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/427 ,  H01L25/0655 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/481 ,  H01L2224/16235

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.

公开(公告)号：US11004816B2

公开(公告)日：2021-05-11

申请号：US16553179

申请日：2019-08-28

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

公开(公告)号：US20210118860A1

公开(公告)日：2021-04-22

申请号：US16884051

申请日：2020-05-27

Applicant: Industrial Technology Research Institute

Inventor： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

IPC: H01L25/18 ,  H01L31/0203 ,  H01L23/00

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

公开(公告)号：US09391049B2

公开(公告)日：2016-07-12

申请号：US14561546

申请日：2014-12-05

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Chau-Jie Zhan

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y10T428/24149 ,  H01L2224/81 ,  H01L2924/00

Abstract: A molding package assembly is provided, which includes a substrate and first and second molding packages stacked on the substrate. Each of the first and second molding packages has a semiconductor element, an anti-warping structure disposed around a periphery of the semiconductor element, a molding material encapsulating the semiconductor element and the anti-warping structure, and a protection layer formed on the semiconductor element, the molding material and the anti-warping structure. The anti-warping structure facilitates to prevent warping of the molding package assembly during a molding process.

Abstract translation: 提供了一种成型包装组件，其包括基板和堆叠在基板上的第一和第二模制包装。 第一和第二成型包装件中的每一个具有半导体元件，围绕半导体元件的周围设置的防翘曲结构，封装半导体元件和抗翘曲结构的成型材料以及形成在半导体元件上的保护层 ，成型材料和抗翘曲结构。 防翘曲结构便于在模制过程中防止模制包装组件翘曲。