公开(公告)号：US12009341B2

公开(公告)日：2024-06-11

申请号：US17564197

申请日：2021-12-28

Applicant: Industrial Technology Research Institute

Inventor： Po-Kai Chiu ,  Sheng-Tsai Wu ,  Yu-Min Lin ,  Wen-Hung Liu ,  Ang-Ying Lin ,  Chang-Sheng Chen

IPC: H01L31/0203 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

公开(公告)号：US11569217B2

公开(公告)日：2023-01-31

申请号：US17568740

申请日：2022-01-05

Applicant: Industrial Technology Research Institute

Inventor： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

IPC: H01L31/0203 ,  H01L25/18 ,  H01L23/00

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

公开(公告)号：US11424190B2

公开(公告)日：2022-08-23

申请号：US17005310

申请日：2020-08-27

Applicant: Industrial Technology Research Institute

Inventor： Chao-Jung Chen ,  Yu-Min Lin ,  Sheng-Tsai Wu ,  Shin-Yi Huang ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Yuan-Yin Lo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

公开(公告)号：US20210111126A1

公开(公告)日：2021-04-15

申请号：US17065521

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Ang-Ying Lin ,  Yu-Min Lin ,  Shin-Yi Huang ,  Sheng-Tsai Wu ,  Yuan-Yin Lo ,  Tzu-Hsuan Ni ,  Chao-Jung Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

公开(公告)号：US20210111125A1

公开(公告)日：2021-04-15

申请号：US17005310

申请日：2020-08-27

Applicant: Industrial Technology Research Institute

Inventor： Chao-Jung Chen ,  Yu-Min Lin ,  Sheng-Tsai Wu ,  Shin-Yi Huang ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Yuan-Yin Lo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

公开(公告)号：US11587905B2

公开(公告)日：2023-02-21

申请号：US17065527

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20210111153A1

公开(公告)日：2021-04-15

申请号：US17065527

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20200075519A1

公开(公告)日：2020-03-05

申请号：US16553179

申请日：2019-08-28

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Tao-Chih Chang ,  Wei-Chung Lo

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31

Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

公开(公告)号：US12074137B2

公开(公告)日：2024-08-27

申请号：US18166493

申请日：2023-02-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/50 ,  H01L2225/06548 ,  H01L2924/181

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US12027470B2

公开(公告)日：2024-07-02

申请号：US17547200

申请日：2021-12-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/568 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17

Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.