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    MULTI-TILE GRAPHICS PROCESSING UNIT
    31.
    发明申请
    MULTI-TILE GRAPHICS PROCESSING UNIT 有权

    公开(公告)号：US20230051227A1

    公开(公告)日：2023-02-16

    申请号：US17978426

    申请日：2022-11-01

    Applicant: Intel Corporation

    Inventor： Michal Mrozek ,  Bartosz Dunajski ,  Ben Ashbaugh ,  Brandon Fliflet

    IPC: G06T1/60 ,  G06T1/20 ,  G06F3/06

    Abstract: An apparatus to facilitate processing in a multi-tile device is disclosed. In one embodiment, the apparatus includes a graphics processor comprising a first semiconductor die including a first high-bandwidth memory (HBM) device, a second semiconductor die including a second HBM device, and a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement. The third semiconductor die includes a graphics processing resource and a cache coupled with the graphics processing resource. The cache is configurable to cache data associated with memory accessed by the graphics processing resource and the graphics processing resource includes a general-purpose graphics processor core and a tensor core.

    Partial write management in a multi-tiled compute engine
    39.
    发明授权
    Partial write management in a multi-tiled compute engine 有权

    公开(公告)号：US10802967B1

    公开(公告)日：2020-10-13

    申请号：US16457088

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  James Valerio ,  Ben Ashbaugh ,  Lakshminarayanan Striramassarma

    IPC: G06F12/0815 ,  G06F12/0811 ,  G06F3/06 ,  G06F9/38 ,  G06F9/54

    Abstract: Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.

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