公开(公告)号：US09780782B2

公开(公告)日：2017-10-03

申请号：US14498794

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kuljit S Bains ,  Nadav Bonen

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G06F13/40

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US20170093400A1

公开(公告)日：2017-03-30

申请号：US14865866

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

IPC: H03K19/0175 ,  G06F3/06 ,  G06F13/16

CPC classification number: H03K19/017545 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1668

Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

公开(公告)号：US09582430B2

公开(公告)日：2017-02-28

申请号：US14671927

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Zvika Greenfield ,  Nadav Bonen ,  Israel Diamand

IPC: G06F13/00 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/62

Abstract: Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may include one or more processing cores for processing of data, and a cache memory to cache data from a main memory for the one or more processing cores, the cache memory including a first cache portion, the first cache portion including a direct-mapped cache, and a second cache portion, the second cache portion including a multi-way cache. The cache memory includes asymmetric sets in the first cache portion and the second cache portion, the first cache portion being larger than the second cache portion. A coordinated replacement policy for the cache memory provides for replacement of data in the first cache portion and the second cache portion.

Abstract translation: 实施例通常涉及包括直接映射高速缓存部分和多路高速缓存部分的非对称集合组合高速缓存。 处理器可以包括用于处理数据的一个或多个处理核心，以及高速缓存存储器，用于从一个或多个处理核心的主存储器缓存数据，高速缓存存储器包括第一高速缓存部分，第一高速缓存部分包括直接 - 映射的高速缓存和第二高速缓存部分，所述第二高速缓存部分包括多路高速缓存。 高速缓存存储器包括第一高速缓存部分和第二高速缓存部分中的非对称集合，第一高速缓存部分大于第二高速缓存部分。 缓存存储器的协调替换策略提供了第一高速缓存部分和第二高速缓存部分中的数据的替换。

公开(公告)号：US20160254044A1

公开(公告)日：2016-09-01

申请号：US14865754

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert ,  Nadav Bonen ,  Tomer Levy

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract translation: 存储器子系统刷新管理使得命令能够使用单个命令访问跨不同银行组的一个或多个识别的银行。 每个银行组分别单独发送在单独的银行组中发送标识银行或银行的命令，该命令可以导致存储设备访问不同银行组中的银行。 该命令可以是刷新命令。 该命令可以是预充电命令。