公开(公告)号：US20150311257A1

公开(公告)日：2015-10-29

申请号：US14264280

申请日：2014-04-29

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Federico Nardi ,  Ryan C. Clarke ,  Tim Minvielle ,  Yun Wang

IPC: H01L27/24 ,  H01L21/02 ,  H01L21/265 ,  H01L45/00 ,  H01L29/08

CPC classification number: H01L27/2463 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L27/2436 ,  H01L29/0847 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped.

Abstract translation: 提供了具有可操作为其他器件的电极的延伸导电层的电阻随机存取存储器（ReRAM）单元，以及制造这样的单元和其它器件的方法。 ReRAM单元的导电层延伸超过由可变电阻层限定的单元边界。 延伸部分可以用于可控制通过电池或其他装置的电流的FET的源极或漏极区域。 扩展导电层也可以作为另一电阻式开关电池或不同器件的电极工作。 延伸的导电层可以由掺杂的硅形成。 ReRAM单元的可变电阻层可以位于与FET的栅极电介质层相同的水平上。 可变电阻层和栅极电介质层可以具有相同的厚度并且共享共同的材料，尽管它们可以是不同的掺杂。

公开(公告)号：US20150179930A1

公开(公告)日：2015-06-25

申请号：US14138462

申请日：2013-12-23

Applicant: Intermolecular Inc.

Inventor： Federico Nardi ,  Yun Wang

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction. This combination of the two Schottky barriers provides current compliance during set operations and limits undesirable current overshoots during reset operations. The Schottky barriers' heights are configured to match the resistive switching characteristics of the cell. Conductive layers of the ReRAM cells operable as electrodes may be used to form these Schottky barriers together with semiconductor layers. These semiconductor layers may be different components from a variable resistance layer and, in some embodiments, may be separated by intermediate conductive layers from the variable resistance layers.

Abstract translation: 提供了具有肖特基势垒的电阻随机存取存储器（ReRAM）单元和制造这种ReRAM单元的方法。 具体来说，ReRAM单元包括两个肖特基势垒，一个势垒限制了沿一个方向通过可变电阻层的电流，另一个势垒限制了相反方向上的电流。 两个肖特基势垒的这种组合在设置操作期间提供电流兼容性，并在复位操作期间限制不期望的电流过冲。 肖特基势垒的高度配置为匹配电池的电阻开关特性。 可用作电极的ReRAM单元的导电层可以用于与半导体层一起形成这些肖特基势垒。 这些半导体层可以是与可变电阻层不同的部件，并且在一些实施例中可以由可变电阻层的中间导电层分离。

公开(公告)号：US20150170923A1

公开(公告)日：2015-06-18

申请号：US14133546

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Federico Nardi ,  Randall J. Higuchi ,  Robert A. Huertas ,  Yun Wang

IPC: H01L21/306

CPC classification number: H01L21/32134 ,  H01L21/28123 ,  H01L21/32139 ,  H01L28/20 ,  H01L29/66545

Abstract: Selective wet etching is used to produce feature sizes of reduced width in semiconductor devices. An initial patterning step (e.g., photolithography) forms a pillar of an initial width from at least a selected first layer and an overlayer. A wet etchant that is selective to the selected layer undercuts the sidewalls of the selected layer to a smaller width while leaving at least part of the overlayer in place to protect the top surface of the selected layer. The selected layer becomes a narrow “stem” within the pillar, and may have dimensions below the resolution limit of the technique used for the initial patterning. For some devices, voids may be intentionally left in a fill layer around the stem for electrical or thermal insulation.

Abstract translation: 选择性湿蚀刻用于制造半导体器件中宽度减小的特征尺寸。 初始构图步骤（例如，光刻）从至少所选择的第一层和覆盖层形成初始宽度的柱。 对所选择的层选择性的湿蚀刻剂将所选层的侧壁切割成更小的宽度，同时使覆盖层的至少一部分保留在适当位置以保护所选择的层的顶表面。 所选择的层在柱内成为窄的“茎”，并且可以具有低于用于初始图案化的技术的分辨率极限的尺寸。 对于一些设备，可能有意将空隙留在阀杆周围的填充层中进行电气或绝热。

公开(公告)号：US08872152B2

公开(公告)日：2014-10-28

申请号：US13714106

申请日：2012-12-13

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Federico Nardi ,  Yun Wang

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1608

Abstract: A nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, and methods of forming the same. A nonvolatile memory element includes a first electrode layer formed on a substrate, a resistive switching layer formed on the first electrode layer, and a second electrode layer. The resistive switching layer comprises a metal oxide and is disposed between the first electrode layer and the second electrode layer. The elemental metal selected for each of the first and second electrode layers is the same metal as selected to form the metal oxide resistive switching layer. The use of common metal materials within the memory element eliminates the growth of unwanted and incompatible native oxide interfacial layers that create undesirable circuit impedance.

Abstract translation: 一种非易失性存储器件，其包含具有改进的器件切换性能和寿命的电阻式开关存储元件及其形成方法。 非易失性存储元件包括形成在基板上的第一电极层，形成在第一电极层上的电阻开关层和第二电极层。 电阻开关层包括金属氧化物，并且设置在第一电极层和第二电极层之间。 为第一和第二电极层中的每一个选择的元素金属与所选择的金属相同，以形成金属氧化物电阻式开关层。 在记忆元件内部使用普通金属材料消除了不希望的和不相容的天然氧化物界面层的生长，产生不希望的电路阻抗。

公开(公告)号：US20140192586A1

公开(公告)日：2014-07-10

申请号：US13738524

申请日：2013-01-10

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Federico Nardi ,  Yun Wang

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/71 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149

Abstract: Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation.

Abstract translation: 提供形成阵列的电阻随机存取存储器（ReRAM）单元和操作这样的单元和阵列的方法。 相同阵列的ReRAM单元可以具有相同的结构，例如具有相同的底部电极，顶部电极和电阻式开关层。 然而，这些电池可以以不同的方式操作。 例如，可以使用比其他单元更低的开关电压来重新切换一些ReRAM单元。 细胞也可能具有不同的数据保留特征。 这些差异可以通过对于不同的单元使用不同的成形操作来实现，或者更具体地，针对不同的单元流动形成不同方向的电流。 形成在电阻开关层内的所得导电路径被认为在不同的电极接口处，即在所谓的开关区域内或附近切换。 在一些实施例中，即使在初始形成之后，ReRAM单元的切换区也可能改变。