中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.029 seconds)

    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same
    2.
    发明申请
    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same 审中-公开
    使用它的材料和器件中形成铁电相的方法

    公开(公告)号：US20160181091A1

    公开(公告)日：2016-06-23

    申请号：US14576853

    申请日：2014-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Sandip Niyogi ,  Sergey Barabash ,  Federico Nardi ,  Dipankar Pramanik

    IPC: H01L21/02

    CPC classification number: H01L29/516

    Abstract: Embodiments provided herein describe systems and methods for forming ferroelectric materials. A trench body may be provided. A trench may be formed in the trench body. A dielectric material and a filler material may be deposited within the trench. The filler material may be heated such that a stress is exerted on the dielectric material before the dielectric material is heated to generate a ferroelectric phase within the dielectric material. A non-contiguous layer may be formed above a substrate. A second layer including a high-k dielectric material may be formed above the first layer. The high-k dielectric material may be heated to generate a ferroelectric phase within the high-k dielectric material.

    Abstract translation: 本文提供的实施例描述了用于形成铁电材料的系统和方法。 可以提供沟槽体。 可以在沟槽体中形成沟槽。 介电材料和填充材料可以沉积在沟槽内。 填充材料可以被加热，使得在介电材料被加热之前在电介质材料上施加应力以在电介质材料内产生铁电相。 可以在衬底之上形成不连续的层。 可以在第一层之上形成包括高k电介质材料的第二层。 可以加热高k介电材料以在高k电介质材料内产生铁电相。

    Resistive switching sample and hold
    3.
    发明授权
    Resistive switching sample and hold 有权
    电阻式开关采样和保持

    公开(公告)号：US09245649B2

    公开(公告)日：2016-01-26

    申请号：US14108877

    申请日：2013-12-17

    Applicant: Intermolecular Inc.

    Inventor： Federico Nardi ,  Ryan C. Clarke ,  Yun Wang

    IPC: G11C27/02 ,  G11C13/00

    CPC classification number: G11C27/02 ,  G11C13/0002 ,  G11C13/0007

    Abstract: A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

    Abstract translation: 非易失性采样和保持电路可以包括电阻开关电路，采样电路，复位电路和转换器电路。 电阻开关电路可操作以接受输入电压Vg，并且提供对应于输入信号Vg的电阻响应Rrs。 采样电路可以用于对诸如输入电压Vin的输入信号进行采样，以提供采样电压Vg。 复位电路可以用于将电阻式开关电路复位到高电阻状态。 转换器电路可操作以将电阻开关电路转换成输出电压。 新颖的采样和保持电路可以没有与电荷注入相关的问题，无需建立时间和瞬间采样时间，以及潜在的无限延时时间。

    Resistive Switching Sample and Hold
    4.
    发明申请
    Resistive Switching Sample and Hold 有权
    电阻式开关采样和保持

    公开(公告)号：US20150170760A1

    公开(公告)日：2015-06-18

    申请号：US14108877

    申请日：2013-12-17

    Applicant: Intermolecular Inc.

    Inventor： Federico Nardi ,  Ryan C. Clarke ,  Yun Wang

    IPC: G11C27/02

    CPC classification number: G11C27/02 ,  G11C13/0002 ,  G11C13/0007

    Abstract: A nonvolatile sample and hold circuit can include a resistive switching circuit, a sample circuit, a reset circuit, and a converter circuit. The resistive switching circuit can be operable to accept an input voltage Vg, and provide a resistance response Rrs that corresponds to the input signal Vg. The sampling circuit can be operable to sample an input signal such as an input voltage Vin, to provide a sampled voltage Vg. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The converter circuit can be operable to convert the resistive switching circuit to an output voltage. The novel sample and hold circuit can have no issues related to charge injection, no settling time and instantaneous sampling time, together with potentially infinite hold time.

    Abstract translation: 非易失性采样和保持电路可以包括电阻开关电路，采样电路，复位电路和转换器电路。 电阻开关电路可操作以接受输入电压Vg，并且提供对应于输入信号Vg的电阻响应Rrs。 采样电路可以用于对诸如输入电压Vin的输入信号进行采样，以提供采样电压Vg。 复位电路可以用于将电阻式开关电路复位到高电阻状态。 转换器电路可操作以将电阻开关电路转换成输出电压。 新颖的采样和保持电路可以没有与电荷注入相关的问题，无需建立时间和瞬间采样时间，以及潜在的无限延时时间。

    Resistive random access memory cells having variable switching characteristics
    5.
    发明授权
    Resistive random access memory cells having variable switching characteristics 有权
    具有可变开关特性的电阻式随机存取存储器单元

    公开(公告)号：US09047940B2

    公开(公告)日：2015-06-02

    申请号：US13738524

    申请日：2013-01-10

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Federico Nardi ,  Yun Wang

    IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

    CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/52 ,  G11C2213/71 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149

    Abstract: Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation.

    Abstract translation: 提供形成阵列的电阻随机存取存储器（ReRAM）单元和操作这样的单元和阵列的方法。 相同阵列的ReRAM单元可以具有相同的结构，例如具有相同的底部电极，顶部电极和电阻式开关层。 然而，这些电池可以以不同的方式操作。 例如，可以使用比其他单元更低的开关电压来重新切换一些ReRAM单元。 细胞也可能具有不同的数据保留特征。 这些差异可以通过对于不同的单元使用不同的成形操作来实现，或者更具体地，针对不同的单元流动形成不同方向的电流。 形成在电阻开关层内的所得导电路径被认为在不同的电极接口处，即在所谓的开关区域内或附近切换。 在一些实施例中，即使在初始形成之后，ReRAM单元的切换区也可能改变。

    Stacked Bi-layer as the low power switchable RRAM
    7.
    发明申请
    Stacked Bi-layer as the low power switchable RRAM 有权
    堆叠双层作为低功率可切换RRAM

    公开(公告)号：US20150188045A1

    公开(公告)日：2015-07-02

    申请号：US14140683

    申请日：2013-12-26

    Applicant: Intermolecular Inc.

    Inventor： Yun Wang ,  Federico Nardi ,  Milind Weling

    IPC: H01L45/00

    CPC classification number: H01L45/1266 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.

    Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 电阻式开关非易失性存储单元可以包括设置的第一层。 第一层可以用作底部电极。 电阻式开关非易失性存储单元还可以包括设置在第一层上的第二层。 第二层可以用作电阻性开关层，其被配置为在第一电阻状态和第二电阻状态之间切换。 电阻式开关非易失性存储单元可以包括设置在第二层上的第三层。 第三层可以用作电阻层，其被配置为至少部分地确定电阻式开关非易失性存储元件的电阻率。 第三层可以包括半金属材料。 电阻式开关非易失性存储单元可以包括可以用作顶部电极的第四层。

    Voltage controlling assemblies including variable resistance devices
    8.
    发明授权
    Voltage controlling assemblies including variable resistance devices 有权
    电压控制组件包括可变电阻器件

    公开(公告)号：US09054634B1

    公开(公告)日：2015-06-09

    申请号：US14140821

    申请日：2013-12-26

    Applicant: Intermolecular Inc.

    Inventor： Federico Nardi ,  Yun Wang

    IPC: H03K3/26 ,  H03B7/06 ,  H03K3/0231 ,  G11C11/16

    CPC classification number: H03B7/06 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0038 ,  G11C13/0061 ,  H03K3/0231

    Abstract: Provided are voltage controlling assemblies that may be operable as clocks and/or oscillators. A voltage controlling assembly may include a comparator and a variable resistance device connected to one differential signal node of the comparator. The other node may be connected to a capacitor. Alternatively, no capacitors may be used in the assembly. During operation of the voltage controlling assembly, the variable resistance device changes its resistance between two different resistive states. The change from a low to a high resistive state may be associated with a voltage spike at the differential signal node of the comparator and trigger a response from the comparator. This resistance change may have a delay determining an operating frequency of the voltage controlling assembly. Specifically, the variable resistance device in the low resistive state may be kept for a period of time at a certain voltage before it switches into the high resistive state.

    Abstract translation: 提供了可以用作时钟和/或振荡器的电压控制组件。 电压控制组件可以包括连接到比较器的一个差分信号节点的比较器和可变电阻器件。 另一个节点可以连接到电容器。 或者，组件中不能使用电容器。 在电压控制组件的操作期间，可变电阻器件改变其在两个不同电阻状态之间的电阻。 从低电阻状态到高电阻状态的变化可能与比较器的差分信号节点处的电压尖峰相关联，并且触发来自比较器的响应。 该电阻变化可以具有确定电压控制组件的工作频率的延迟。 具体地说，低电阻状态的可变电阻器件在切换到高电阻状态之前，可以将其保持一定时间。

    Vertical oxide-oxide interface for forming-free, low power and low variability RRAM devices
    9.
    发明授权
    Vertical oxide-oxide interface for forming-free, low power and low variability RRAM devices 有权
    垂直氧化物 - 氧化物接口，用于无成型，低功耗和低变化性的RRAM器件

    公开(公告)号：US09018037B1

    公开(公告)日：2015-04-28

    申请号：US14098263

    申请日：2013-12-05

    Applicant: Intermolecular, Inc.

    Inventor： Federico Nardi ,  Randall J. Higuchi ,  Robert A. Huertas ,  Yun Wang

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/08 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1666

    Abstract: Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.

    Abstract translation: 形成具有垂直接口的电阻式开关层可以产生沿着两个电极之间的界面限制的缺陷。 限制缺陷可以形成用于灯丝形成和溶解的预定区域，导致低功率电阻切换和低编程电压或电流变化。 此外，由于限制缺陷的存在，可以省略电阻式存储器件的灯丝形成工艺。

Patent Agency Ranking