公开(公告)号：US09385224B2

公开(公告)日：2016-07-05

申请号：US14458906

申请日：2014-08-13

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/76 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/66

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

摘要翻译： 公开了一种集成电路，其包括具有在单通道器件区域中覆盖衬底结构的单个共享异质结构的第一部分的单通道器件，以及与单个共用异质结构的第一部分接触的栅极接触。 集成电路还包括多通道器件，其包括覆盖多通道器件区域中的衬底结构的单个共享异质结构的第二部分，覆盖在单个共用异质结构的第二部分上的阻挡层，以及覆盖在阻挡层上的超晶格结构， 超晶格结构包括多个异质结构。 单个共享异质结构中的隔离区域将单通道器件与多通道器件隔离。

公开(公告)号：US07795647B2

公开(公告)日：2010-09-14

申请号：US11727955

申请日：2007-03-29

申请人： Garrett A. Storaska ,  Robert S. Howell ,  Harvey C. Nathanson ,  Francis William Hopwood

发明人： Garrett A. Storaska ,  Robert S. Howell ,  Harvey C. Nathanson ,  Francis William Hopwood

IPC分类号： H01L29/76

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/78603 ,  H01L29/78696

摘要： A curled transistor comprises a coiled semiconductor substrate having a plurality of concentrically curled layers. Source and drain regions are configured on a portion of the coiled semiconductor substrate, and a gate dielectric is positioned between the source and drain regions. A first set of metallic contacts electrically couple to the source region on the coiled semiconductor substrate and a second set of metallic contacts electrically couple to the drain region on the coiled semiconductor substrate.

摘要翻译： 卷曲晶体管包括具有多个同心卷曲层的螺旋半导体衬底。 源极和漏极区域被配置在线圈化的半导体衬底的一部分上，并且栅极电介质位于源极和漏极区域之间。 第一组金属触点电耦合到卷绕的半导体衬底上的源极区域，以及第二组金属触点，电耦合到线圈化的半导体衬底上的漏极区域。

公开(公告)号：US20100224957A1

公开(公告)日：2010-09-09

申请号：US12693875

申请日：2010-01-26

申请人： Garrett A. STORASKA ,  Robert S. Howell

发明人： Garrett A. STORASKA ,  Robert S. Howell

IPC分类号： H01L27/08

CPC分类号： H01L27/1203 ,  B81C1/0019 ,  B82Y10/00 ,  B82Y30/00 ,  H01F41/041 ,  H01L21/84 ,  H01L27/10

摘要： Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include microscopic electro-mechanical systems (MEMS) devices including nanocoil mirrors, nanocoil actuators and nanocoil antenna arrays. Inductors or traveling wave tubes fabricated from nanocoils are also included. A method for fabricating nanocoils with a desired pitch includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

摘要翻译： 纳米线技术的新应用和制造纳米线的新方法用于这些应用和其他应用。 这样的应用包括微观机电系统（MEMS）装置，包括纳米油镜，纳米线驱动器和纳米线圈天线阵列。 还包括由纳米体系制造的电感器或行波管。 用于制造具有期望间距的纳米线圈的方法包括确定制造的纳米线圈的期望间距，选择卷取臂取向，其中卷取臂取向是卷绕臂之间的臂角，下面基底的结晶取向，由此卷取臂取向影响制造的纳米线的间距， 以选定的卷取臂取向构图卷取臂结构，以及释放卷取臂，从而形成制造的纳米油。

公开(公告)号：US07710235B2

公开(公告)日：2010-05-04

申请号：US11524245

申请日：2006-09-21

申请人： Garrett A. Storaska ,  Robert S. Howell

发明人： Garrett A. Storaska ,  Robert S. Howell

IPC分类号： H01F21/04 ,  H01F27/28

CPC分类号： H01L27/1203 ,  B81C1/0019 ,  B82Y10/00 ,  B82Y30/00 ,  H01F41/041 ,  H01L21/84 ,  H01L27/10

摘要： Novel applications of nanocoil technology and novel methods of fabricating nanocoils for use in such applications and others. Such applications include inductors or traveling wave tubes fabricated from spiral nanocoils. Such applications includes inductors or traveling wave tubes fabricated from a method for fabricating nanocoils with a desired pitch. Such a method includes determining a desired pitch for fabricated nanocoil, selecting coiling arm orientation in which coiling arm orientation is arm angle between coiling arm an crystalline orientation of underlying substrate, whereby coiling arm orientation affects pitch of fabricated nanocoil, patterning coiling arm structure with selected coiling arm orientation, and, releasing coiling arm, whereby fabricated nanocoil is formed.

摘要翻译： 纳米线技术的新应用和制造纳米线的新方法用于这些应用和其他应用。 这种应用包括由螺旋纳米线制造的电感器或行波管。 这样的应用包括由用于制造具有期望间距的纳米线圈的方法制造的电感器或行波管。 这种方法包括确定所制造的纳米线的期望间距，选择卷取臂取向，其中卷取臂取向是卷绕臂之间的臂角，下面的基底的结晶取向之间的夹角，由此卷取臂取向影响制造的纳米线的间距，图案化卷取臂结构与选定的 卷取臂取向，以及释放卷取臂，从而形成制造的纳米油。

公开(公告)号：US20090194870A1

公开(公告)日：2009-08-06

申请号：US12023831

申请日：2008-01-31

申请人： Harvey C. Nathanson ,  Robert M. Young ,  Joseph T. Smith ,  Robert S. Howell ,  Archer S. Mitchell

发明人： Harvey C. Nathanson ,  Robert M. Young ,  Joseph T. Smith ,  Robert S. Howell ,  Archer S. Mitchell

IPC分类号： H01L23/34 ,  H01L35/00

CPC分类号： H01L35/00 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates to a Point Cooler based on a combination of principles, including large area, low current density PN junction cooling, and electron emission from heavily doped shallowly-depleted P tips. Using Junction Cooling rather than thermoelectric cooling enables an all silicon device to be made that favorably competes with the commercial thermoelectric cooling systems. Theoretical values of THOT/TCOLD of 6 or more (in contrast to about 1.5 for other solid state refrigerators) predict this single-stage solid state vacuum electronic cooler can approach 50K at light loading, significantly lower than conventional Bismuth Telluride based thermo electrics. The high Z values for PN junction cooling with wire connection and Tunnel heat extraction opens up solid state vibration-less form fit and function replacement cooling.

摘要翻译： 本公开涉及基于原理组合的点冷却器，包括大面积，低电流密度PN结冷却和来自重掺杂的浅耗尽P尖端的电子发射。 使用接合冷却而不是热电冷却使得所有的硅器件能够被制造成与商业热电冷却系统相竞争。 THOT / TCOLD的理论值为6以上（与其他固态冰箱的1.5倍相比）预测，这种单级固态真空电子式冷却器在轻载时可达到50K，明显低于传统的碲化铋基热电。 通过电线连接和隧道热提取的PN结冷却的高Z值打开固态无振动形式配合和功能更换冷却。

公开(公告)号：US07560322B2

公开(公告)日：2009-07-14

申请号：US11248195

申请日：2005-10-13

申请人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

发明人： Rowland C. Clarke ,  Robert S. Howell ,  Michael E. Aumer

IPC分类号： H01L21/338 ,  H01L21/30

CPC分类号： H01L21/76256 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/735 ,  H01L29/7787

摘要： A substrate arrangement for high power semiconductor devices includes a SiC wafer having a Si layer deposited on a surface of the SiC wafer. An SOI structure having a first layer of Si, an intermediate layer of SiO2 and a third layer of Si, has its third layer of Si bonded to the Si deposited on the SiC wafer, forming a unitary structure. The first layer of Si and the intermediate layer of SiO2 of the SOI are removed, leaving a pure third layer of Si on which various semiconductor devices may be fabricated. The third layer of Si and deposited Si layer may be removed over a portion of the substrate arrangement such that one or more semiconductor devices may be fabricated on the SiC wafer while other semiconductor devices may be accommodated on the pure third layer of Si.

摘要翻译： 用于大功率半导体器件的衬底布置包括在SiC晶片的表面上沉积有Si层的SiC晶片。 具有Si的第一层，SiO 2的中间层和Si的第三层的SOI结构具有与沉积在SiC晶片上的Si结合的第三层Si，形成整体结构。 除去SOI的第一层和SiO 2的中间层，留下可以制造各种半导体器件的纯的第三层Si。 可以在衬底布置的一部分上去除第三层Si和沉积的Si层，使得可以在SiC晶片上制造一个或多个半导体器件，而其他半导体器件可以容纳在纯的第三层Si上。

公开(公告)号：US20090053860A1

公开(公告)日：2009-02-26

申请号：US11524246

申请日：2006-09-21

申请人： Garrett A. Storaska ,  Robert S. Howell

发明人： Garrett A. Storaska ,  Robert S. Howell

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  B81C1/0019 ,  B82Y10/00 ,  B82Y30/00 ,  H01F41/041 ,  H01L21/84 ,  H01L27/10

摘要： A method for fabricating nanocoils and improved nanocoils fabricated therefrom. Embodiments of the method utilizing deep reactive ion etching (DRIE). A method for fabricating nanocoils includes providing a silicon-on-insulator (SOI) wafer, in which SOI wafer includes buried oxide layer, patterning one or more devices into a layer of silicon on top of the buried oxide layer, depositing tensile stressed nitride layer on the top silicon layer, patterning coiling arm structure on top silicon layer, patterning an overlapping etch window mask on bottom side of SOI wafer using, in which patterning overlapping etch window mask removes SOI wafer and exposes buried oxide layer in width greater than coiling arm structure, and releasing coiling arm structure so that coiling arm coils to form nanocoil. In embodiments, DRIE is utilized to pattern the overlapping etch window mask.

摘要翻译： 一种用于制造纳米线和由其制造的改进的纳米薄膜的方法。 利用深反应离子蚀刻（DRIE）的方法的实施例。 制造纳米线的方法包括提供绝缘体上硅（SOI）晶片，其中SOI晶片包括掩埋氧化物层，将一个或多个器件图案化成掩埋氧化物层顶部的硅层，沉积拉应力氮化物层 在顶层硅层上，在顶部硅层上图案化卷取臂结构，在SOI晶片的底侧上构图重叠的蚀刻窗口掩模，其中图案化重叠的蚀刻窗口掩模移除SOI晶片并使掩埋氧化物层的宽度大于卷取臂 结构和释放卷取臂结构，使卷绕臂线圈形成纳米油。 在实施例中，DRIE用于对重叠的蚀刻窗口掩模进行图案化。