公开(公告)号：US09385224B2

公开(公告)日：2016-07-05

申请号：US14458906

申请日：2014-08-13

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/76 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/66

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

摘要翻译： 公开了一种集成电路，其包括具有在单通道器件区域中覆盖衬底结构的单个共享异质结构的第一部分的单通道器件，以及与单个共用异质结构的第一部分接触的栅极接触。 集成电路还包括多通道器件，其包括覆盖多通道器件区域中的衬底结构的单个共享异质结构的第二部分，覆盖在单个共用异质结构的第二部分上的阻挡层，以及覆盖在阻挡层上的超晶格结构， 超晶格结构包括多个异质结构。 单个共享异质结构中的隔离区域将单通道器件与多通道器件隔离。

公开(公告)号：US09755021B2

公开(公告)日：2017-09-05

申请号：US15186193

申请日：2016-06-17

申请人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

发明人： Karen M. Renaldo ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Harlan Carl Cramer ,  Justin Andrew Parke ,  Matthew Russell King

IPC分类号： H01L29/66 ,  H01L29/15 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/302 ,  H01L29/423 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/205 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.

公开(公告)号：US10854600B2

公开(公告)日：2020-12-01

申请号：US16577629

申请日：2019-09-20

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L21/338 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

公开(公告)号：US09711615B2

公开(公告)日：2017-07-18

申请号：US15222039

申请日：2016-07-28

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/20

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US10084075B2

公开(公告)日：2018-09-25

申请号：US15624445

申请日：2017-06-15

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/15

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

公开(公告)号：US09472634B2

公开(公告)日：2016-10-18

申请号：US15065298

申请日：2016-03-09

申请人： Eric J Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Ronald G Freitag ,  Karen Marie Renaldo

发明人： Eric J Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Ronald G Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L29/42316 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7783

摘要： A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.

摘要翻译： 提供了一种装置，其包括设置在第一区域中并覆盖基部结构的第一柱体，以及设置在第二区域中并且覆盖基部结构并与设备区域与第一柱体间隔开的第二柱体。 桥接器设置在设备区域中，第一端连接到第一柱，第二端连接到第二柱。 桥梁包括顶部，侧面和底部。 该桥由一个或多个异质结构形成，具有从底部延伸到下面的结构的底切开口。 四面导电接触围绕其顶部，其侧面及其底部沿其长度的至少一部分在第一和第二端之间围绕并基本上围绕桥。

公开(公告)号：US10468406B2

公开(公告)日：2019-11-05

申请号：US14509750

申请日：2014-10-08

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/15 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.

公开(公告)号：US09466679B2

公开(公告)日：2016-10-11

申请号：US14459006

申请日：2014-08-13

申请人： Eric J. Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Karen Marie Renaldo ,  Ronald G. Freitag

发明人： Eric J. Stewart ,  Howell George Henry ,  Robert S. Howell ,  Matthew Russell King ,  Justin Andrew Parke ,  Bettina Nechay ,  Harlan Carl Cramer ,  Karen Marie Renaldo ,  Ronald G. Freitag

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/42316 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7783

摘要： A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.

公开(公告)号：US09419120B2

公开(公告)日：2016-08-16

申请号：US14533752

申请日：2014-11-05

申请人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Bettina A. Nechay ,  Shalini Gupta ,  Matthew Russell King ,  Eric J. Stewart ,  Robert S. Howell ,  Justin Andrew Parke ,  Harlan Carl Cramer ,  Howell George Henry ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/778 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7785 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/157 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

摘要： A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

摘要翻译： 提供了一种晶体管器件，其包括基底结构和覆盖在基底结构上的超晶格结构，并且包括具有倾斜侧壁的多通道脊。 多通道脊包括多个异质结构，每个异质结构形成多通道脊的通道，其中至少一个异质结构的参数相对于多个异质结构中的其它异质结构而变化。 晶体管器件还包括三边形栅极接触，其沿着其深度的至少一部分包围并基本上围绕多通道脊的顶部和侧面。

公开(公告)号：US20090250808A1

公开(公告)日：2009-10-08

申请号：US12416711

申请日：2009-04-01

申请人： Randall D. Lewis ,  Harlan Carl Cramer

发明人： Randall D. Lewis ,  Harlan Carl Cramer

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L23/34 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32014 ,  H01L2924/0001 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2924/01031 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/01033 ,  H01L2224/29099

摘要： A semiconductor package (M) includes a semiconductor substrate layer (100) having a first side or upper surface (120) and a second side or lower surface or backplane (104) opposite the first side (120). A heat producing active area (102) is formed associated with the first side (120) of the semiconductor substrate layer (100). A die attachment member (106) is formed in contact with the second side (104) of the semiconductor substrate layer (100) and extends over less than all of the second side (104) of the semiconductor substrate layer (100). The die attachment material (106) is essentially uniformly disposed opposite of the heat producing area (102) with relation to the semiconductor substrate layer (100).

摘要翻译： 半导体封装（M）包括具有第一侧面或上表面（120）以及与第一侧（120）相对的第二侧面或下表面或背板（104）的半导体衬底层（100）。 形成与半导体衬底层（100）的第一侧（120）相关联的发热活性区域（102）。 形成与半导体衬底层（100）的第二侧（104）接触并且在半导体衬底层（100）的小于全部第二侧（104）上延伸的管芯附接构件（106）。 相对于半导体衬底层（100），芯片附着材料（106）基本上均匀地布置成与发热区域（102）相对。