公开(公告)号：US20090237103A1

公开(公告)日：2009-09-24

申请号：US12051868

申请日：2008-03-20

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC分类号： G01R31/26 ,  H01L23/00 ,  G06F17/50

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

摘要翻译： 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US08836835B2

公开(公告)日：2014-09-16

申请号：US12897295

申请日：2010-10-04

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Richard J. Rassel

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Richard J. Rassel

IPC分类号： H04N5/335 ,  H04N5/359 ,  H01L27/146 ,  H04N5/3745

CPC分类号： H04N5/3595 ,  H01L27/14603 ,  H01L27/14609 ,  H04N5/3532 ,  H04N5/359 ,  H04N5/3745 ,  H04N5/378

摘要： A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

摘要翻译： 提供了具有用于泄漏消除的保持节点的参考像素传感器单元（例如，全局快门），制造方法和设计结构。 像素阵列包括在有源光感测区域局部分散的一个或多个参考像素传感器单元。 一个或多个参考像素传感器单元提供用于校正由于有源光感测区域内的局部性而变化的光子产生的泄漏信号的参考信号。

公开(公告)号：US08009216B2

公开(公告)日：2011-08-30

申请号：US12174289

申请日：2008-07-16

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/37452 ,  H04N5/2355

摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

公开(公告)号：US07915056B2

公开(公告)日：2011-03-29

申请号：US12051868

申请日：2008-03-20

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

摘要翻译： 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US07821553B2

公开(公告)日：2010-10-26

申请号：US11275417

申请日：2005-12-30

申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N9/083

CPC分类号： H04N9/045

摘要： A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.

摘要翻译： 图像传感器中的像素阵列，图像传感器和包括图像传感器的数字照相机。 图像传感器包括具有彩色像素和未滤波（无滤色器）像素的像素阵列。 每个未过滤的像素占据一个或多个阵列位置。 彩色像素可以布置在不间断的行和列中，其中未过滤的像素布置在不间断的行和列之间。 图像传感器可以在CMOS中，未滤色像素降低低光噪声并改善低光灵敏度。

公开(公告)号：US08618588B2

公开(公告)日：2013-12-31

申请号：US12915888

申请日：2010-10-29

申请人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H04N5/238 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/3591

摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

摘要翻译： 防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

公开(公告)号：US20080111159A1

公开(公告)日：2008-05-15

申请号：US11560019

申请日：2006-11-15

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

IPC分类号： H01L31/101 ,  H01L29/765 ,  H01L23/52 ,  H01L21/339

CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

公开(公告)号：US07928527B2

公开(公告)日：2011-04-19

申请号：US12132875

申请日：2008-06-04

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

IPC分类号： H01L29/72

CPC分类号： H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

摘要： A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

摘要翻译： 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：US07825416B2

公开(公告)日：2010-11-02

申请号：US12423055

申请日：2009-04-14

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

IPC分类号： H01L29/786

CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

公开(公告)号：US20090224349A1

公开(公告)日：2009-09-10

申请号：US12423055

申请日：2009-04-14

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

IPC分类号： H01L31/0232 ,  H01L31/0224

CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。