公开(公告)号：US20140003147A1

公开(公告)日：2014-01-02

申请号：US13537551

申请日：2012-06-29

申请人： Deepanshu Dutta ,  Ken Oowada ,  Koichi Nishimura ,  Yingda Dong

发明人： Deepanshu Dutta ,  Ken Oowada ,  Koichi Nishimura ,  Yingda Dong

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/16 ,  G11C16/344

摘要： In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.

摘要翻译： 关于非易失性存储元件块的擦除操作，确定块是部分地还是不完全编程的。 部分编程的程度可以通过确定最高编程字线的预擦除读取操作来确定，或者确定在源侧字线的小子集之上的字线子集中是否存在编程存储元件。 由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。 在一种方法中，通过在块被部分编程时调整感测参数，擦除验证测试变得更严格。 在另一种方法中，块可以被擦除之前被编程。 或者，可以应用不跟随擦除验证测试的额外擦除脉冲。

公开(公告)号：US08611157B2

公开(公告)日：2013-12-17

申请号：US13335524

申请日：2011-12-22

申请人： Deepanshu Dutta

发明人： Deepanshu Dutta

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/3459

摘要： Methods and non-volatile storage systems are provided for using compensation that depends on the temperature at which the memory cells were programmed. Note that the read level compensation may have a component that is not dependent on the memory cells' Tco. That is, the component is not necessarily based on the temperature dependence of the Vth of the memory cells. The compensation may have a component that is dependent on the difference in width of individual Vth distributions of the different states across different temperatures of program verify. This compensation may be used for both verify and read, although a different amount of compensation may be used during read than during verify.

公开(公告)号：US20130070524A1

公开(公告)日：2013-03-21

申请号：US13239194

申请日：2011-09-21

申请人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

发明人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

摘要翻译： 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。

公开(公告)号：US08385132B2

公开(公告)日：2013-02-26

申请号：US12976893

申请日：2010-12-22

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/3418 ,  G11C16/3436

摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.

摘要翻译： 在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。 诸如升高的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。 升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。 施加减速措施的编程脉冲的范围可以自适应地固定或确定。 当位线电压降低时，程序脉冲增量可以下降，然后增加。 被编程为最高目标数据状态的存储元件可以从减速测量中排除。

公开(公告)号：US20120250418A1

公开(公告)日：2012-10-04

申请号：US13523366

申请日：2012-06-14

申请人： Deepanshu Dutta ,  Jeffrey W Lutze

发明人： Deepanshu Dutta ,  Jeffrey W Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile memory system, a multi-phase programming operation is performed in which a drain-side select gate voltage (Vsgd) can be adjusted in different programming phases to accommodate different bit line bias (Vbl) levels. A higher Vbl can be used when Vsgd is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. For example, Vsgd can be higher in an earlier program phase than in a later program phase. The higher Vbl, which is not based on programming speed, can be is applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase, or at other times. The higher Vbl is an additional slow down measure which can be implemented in addition to a programming speed-based slow down measure such as a further raised Vbl which is applied to faster-programming storage elements.

摘要翻译： 在非易失性存储器系统中，执行多相编程操作，其中可以在不同的编程阶段调整漏极侧选择栅极电压（Vsgd）以适应不同的位线偏置（Vbl）电平。 当Vsgd较高时可以使用更高的Vbl，以避免SGD晶体管上的不必要的应力，并降低功耗。 例如，Vsgd可能在较早的程序阶段比在较后的程序阶段更高。 当存储元件的Vth在目标数据状态的下限和上限验证电平之间，或者在整个编程阶段，或者在其他时间时，可以应用不基于编程速度的较高Vbl。 较高的Vbl是一种额外的减速措施，除了基于速度的编程速度减慢措施之外，还可以实现这一措施，例如进一步升高的Vbl，其应用于更快编程的存储元件。

公开(公告)号：US08274838B2

公开(公告)日：2012-09-25

申请号：US12838902

申请日：2010-07-19

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3486 ,  G11C2216/14

摘要： Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.

摘要翻译： 使用编程技术使非易失性存储器件中的阈值电压分布变窄，并且/或编程时间减少，其中具有目标数据状态的存储元件的位线电压被升高，在升压锁定步骤中 在编程电压。 根据其目标数据状态，针对存储元件的不同子集，在编程遍历中的不同时刻对位线电压进行升压。 可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压中的升压的开始和停止。 变化包括使用固定的位线步长，变化的位线步长，数据状态相关的位线步长，不增加一个或多个数据状态的位线的选项以及增加额外位线偏置的选项。

公开(公告)号：US20120127800A1

公开(公告)日：2012-05-24

申请号：US13360103

申请日：2012-01-27

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

摘要翻译： 非易失性存储系统通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的程序干扰，这增加了禁止信道的钳位升压电位以避免程序干扰。 交替的相邻位线对被分组成第一和第二组。 第一组对的非易失性存储元件经受编程脉冲并且在第一迭代次数中的每一个中验证操作，之后第二组对的非易失性存储元件经受编程脉冲并且验证操作 每次迭代次数为次。

公开(公告)号：US08130551B2

公开(公告)日：2012-03-06

申请号：US12751265

申请日：2010-03-31

申请人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

发明人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/14 ,  G11C16/3436

摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.

摘要翻译： 用于非易失性存储器的擦除操作包括第一和第二相。 第一阶段将一系列电压脉冲施加到衬底，其中每个擦除脉冲之后是验证操作。 验证操作使用从最终期望的阈值电压电平偏移的验证电平。 擦除脉冲以幅度升高直到达到最大电平，此时施加最大电平的附加擦除脉冲。 当验证操作通过时，第一阶段结束。 第二阶段施加一个或多个额外的擦除脉冲，其幅度高于第一阶段中的最后一个擦除脉冲，并且其后跟无验证操作。 这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写擦除耐久性，同时仍然实现期望的深度擦除。

公开(公告)号：US20120033500A1

公开(公告)日：2012-02-09

申请号：US12849510

申请日：2010-08-03

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.

摘要翻译： 在非易失性存储器系统中，基于速度的编程速度减慢测量例如升高的位线被应用于更快编程的存储元件。 执行使用来回字线顺序的多相编程操作，其中编程速度数据被存储在一个编程阶段的锁存器中，并且从锁存器读取以用于给定字线的后续编程阶段。 可以通过检测多个存储元件何时达到指定的验证电平，计数基于存储元件的自然阈值电压分布而设置的附加数量的编程脉冲，并且随后执行 一种分离更快和慢速编程存储元件的读取操作。 可以在不同的编程阶段调整漏极侧选择栅极电压，以适应不同的位线偏置电平。

公开(公告)号：US08004900B2

公开(公告)日：2011-08-23

申请号：US12406014

申请日：2009-03-17

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并且驱动或浮动选择栅极电压以精确地控制选择栅极电压以改善写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，选择门在被特定初始级别驱动之后浮动，以达到特定的最佳最终级别。 在另一种方法中，与p阱电压一致，在擦除操作期间，选择栅极以特定电平驱动。 在另一种方法中，选择栅极浮动的开始被延迟，而p阱电压上升。 在另一种方法中，p阱电压以两个步骤升高，并且在第二个斜坡开始之前，选择栅极不浮动。 可以通过提高驱动电压来切断选通门的通孔来实现浮动。