公开(公告)号：US06440799B1

公开(公告)日：2002-08-27

申请号：US09881308

申请日：2001-06-13

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L218242

CPC分类号： H01L21/823878 ,  H01L21/266 ,  H01L21/823842

摘要： The invention includes a method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.

摘要翻译： 本发明包括将掺杂剂注入到半导体结构中的方法，其中在注入第一掺杂剂之后并且在注入第二掺杂剂之前，光致抗蚀剂掩模的横向周边被移位。 本发明还包括具有半导体材料的两个掺杂区域的半导体结构，所述半导体材料由掺杂区域的掺杂区域分开。

公开(公告)号：US06403458B2

公开(公告)日：2002-06-11

申请号：US09055056

申请日：1998-04-03

申请人： Jigish D. Trivedi ,  Michael P. Violette

发明人： Jigish D. Trivedi ,  Michael P. Violette

IPC分类号： H01L214763

CPC分类号： H01L21/76895 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory-metal silicide layer disposed on the nitrogen-rich Ti layer. The local interconnect is especially useful for reducing cratering and consumption of silicon regions underlying the local interconnect.

摘要翻译： 一种制造局部​​互连的方法及由此形成的结构。 该方法通过在衬底的一部分上形成富含氮的上部的Ti层，在Ti层上形成难熔金属层，在难熔金属层上形成Si层，除去Si层的一部分 并加热以形成局部互连结构。 在该过程中，形成用于局部互连的源结构。 该源结构包括具有覆盖在衬底的一部分上的富氮上部的Ti层，覆盖在Ti层上的难熔金属层和覆盖在难熔金属层上的硅层。 得到的局部互连包括设置在衬底的一部分上的硅化钛层，设置在硅化钛层上的富氮Ti层和设置在富氮Ti层上的难熔金属硅化物层。 局部互连特别适用于减少局部互连底层硅片的凹坑和消耗。

公开(公告)号：US06335254B1

公开(公告)日：2002-01-01

申请号：US09635279

申请日：2000-08-09

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/28247 ,  H01L29/4941

摘要： In accordance with an aspect of the invention, a transistor is formed having a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes at least two conductive layers of different conductive materials. One of the two conductive layers is more proximate the gate dielectric layer than the other of the two conductive layers. A source/drain reoxidation is conducted prior to forming the other conductive layer. In another aspect of the invention, a transistor has a transistor gate, a gate dielectric layer and source/drain regions. The transistor gate includes a tungsten layer. A source/drain reoxidation is conducted prior to forming the tungsten layer of the gate. In yet another aspect of the invention, a semiconductor processing method forms a transistor gate having insulative sidewall spacers thereover. After forming the insulative sidewall spacers, an outer conductive tungsten layer of the transistor gate is formed.

摘要翻译： 根据本发明的一个方面，形成具有晶体管栅极，栅极电介质层和源极/漏极区域的晶体管。 晶体管栅极包括至少两个不同导电材料的导电层。 两个导电层之一比栅电介质层更靠近两个导电层中的另一个。 源/漏再氧化在形成另一导电层之前进行。 在本发明的另一方面，晶体管具有晶体管栅极，栅极电介质层和源极/漏极区域。 晶体管栅极包括钨层。 在形成栅极的钨层之前进行源极/漏极再氧化。 在本发明的另一方面，半导体处理方法形成了具有绝缘侧壁间隔物的晶体管栅极。 在形成绝缘侧壁间隔物之后，形成晶体管栅极的外部导电钨层。

公开(公告)号：US08466517B2

公开(公告)日：2013-06-18

申请号：US13445711

申请日：2012-04-12

申请人： Suraj Mathew ,  Jigish D. Trivedi

发明人： Suraj Mathew ,  Jigish D. Trivedi

IPC分类号： H01L27/12

CPC分类号： G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

公开(公告)号：US20120001245A1

公开(公告)日：2012-01-05

申请号：US13231554

申请日：2011-09-13

申请人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

发明人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC分类号： H01L27/108 ,  H01L27/105

CPC分类号： H01L29/66621 ,  H01L27/10876

摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US07659181B2

公开(公告)日：2010-02-09

申请号：US11557014

申请日：2006-11-06

申请人： John A. Smythe, III ,  Jigish D. Trivedi

发明人： John A. Smythe, III ,  Jigish D. Trivedi

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

公开(公告)号：US07538389B2

公开(公告)日：2009-05-26

申请号：US11148853

申请日：2005-06-08

申请人： Suraj Mathew ,  Jigish D. Trivedi

发明人： Suraj Mathew ,  Jigish D. Trivedi

IPC分类号： H01L29/06

CPC分类号： G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

摘要翻译： 在局部绝缘体上形成无电容器DRAM的方法包括以下步骤：提供硅衬底，并且硅衬底阵列限定在硅衬底内。 绝缘体层限定在硅衬底的至少一部分之上，并且在硅柱之间。 围绕绝缘体层上方的硅柱的绝缘体层被限定，并且在绝缘体上硅层内部和上方形成无电容的DRAM。

公开(公告)号：US07517744B2

公开(公告)日：2009-04-14

申请号：US11450661

申请日：2006-06-08

申请人： Suraj Mathew ,  Jigish D. Trivedi

发明人： Suraj Mathew ,  Jigish D. Trivedi

IPC分类号： H01L21/338

CPC分类号： G11C7/00 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/1203 ,  H01L29/7841

摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

公开(公告)号：US07235858B2

公开(公告)日：2007-06-26

申请号：US10882987

申请日：2004-06-30

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

摘要翻译： 一种反熔丝，包括具有基本上平行于第一轴线布置的多个纵向部件的底板，形成在底板上的电介质层以及具有基本平行于第二轴线布置的多个纵向部件的顶板，顶板 形成在电介质层上。 形成在顶板和底板之间的界面处的多个边缘在横跨反熔丝施加编程电压时导致局部电荷浓度的区域。 结果，在底板的角部上形成反熔丝电介质在反熔丝的编程期间增强了电场。 减少编程电压可用于对反熔丝进行编程，并且导致顶板和底板之间的导电路径很可能沿着多个边缘形成。

公开(公告)号：US06809014B2

公开(公告)日：2004-10-26

申请号：US09808261

申请日：2001-03-14

申请人： Suraj J. Mathew ,  Jigish D. Trivedi

发明人： Suraj J. Mathew ,  Jigish D. Trivedi

IPC分类号： H01L21425

CPC分类号： H01L21/823842 ,  H01L27/10873

摘要： An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

摘要翻译： 使用较少掩蔽步骤制造CMOS表面沟道晶体管的改进方法。 可以使用原位掺杂的多晶硅沉积来减少晶体管栅极中的多晶硅耗尽效应的问题。 此外，使用这种方法，可以单独地控制n沟道和p沟道器件之间的每个栅极电介质层中的层数，介电类型和电介质厚度。 该方法还允许使用通常用于制造用于制造表面通道器件的掩埋通道器件的光刻掩模，从而节省了附加掩模的制造。