公开(公告)号：US08450175B2

公开(公告)日：2013-05-28

申请号：US13031829

申请日：2011-02-22

申请人： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

发明人： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

摘要： Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

摘要翻译： 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US09059030B2

公开(公告)日：2015-06-16

申请号：US13269304

申请日：2011-10-07

申请人： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

发明人： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

摘要： A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

摘要翻译： 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地接近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。

公开(公告)号：US06809014B2

公开(公告)日：2004-10-26

申请号：US09808261

申请日：2001-03-14

申请人： Suraj J. Mathew ,  Jigish D. Trivedi

发明人： Suraj J. Mathew ,  Jigish D. Trivedi

IPC分类号： H01L21425

CPC分类号： H01L21/823842 ,  H01L27/10873

摘要： An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

摘要翻译： 使用较少掩蔽步骤制造CMOS表面沟道晶体管的改进方法。 可以使用原位掺杂的多晶硅沉积来减少晶体管栅极中的多晶硅耗尽效应的问题。 此外，使用这种方法，可以单独地控制n沟道和p沟道器件之间的每个栅极电介质层中的层数，介电类型和电介质厚度。 该方法还允许使用通常用于制造用于制造表面通道器件的掩埋通道器件的光刻掩模，从而节省了附加掩模的制造。

公开(公告)号：US06797596B2

公开(公告)日：2004-09-28

申请号：US10232980

申请日：2002-08-29

申请人： Fawad Ahmed ,  Jigish D. Trivedi ,  Suraj J Mathew

发明人： Fawad Ahmed ,  Jigish D. Trivedi ,  Suraj J Mathew

IPC分类号： H01L21425

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28061 ,  H01L29/4933 ,  Y10S438/914 ,  Y10S438/923

摘要： A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate stack assembly comprises a gate oxide layer, a control gate layer, a metal layer, and a dielectric capping layer. A patterned photoresist layer is formed over the unetched transistor gate stack assembly, then each of the capping layer, the metal layer, the control gate layer, and the gate oxide layer is etched to form a plurality of laterally-spaced transistor gate stacks. A screening layer is formed overlying the semiconductor wafer between the transistor gate stacks. A dopant is implanted into the semiconductor wafer through the screening layer, then the screening layer is removed.

公开(公告)号：US08455919B2

公开(公告)日：2013-06-04

申请号：US12838803

申请日：2010-07-19

申请人： Suraj J. Mathew ,  Chandra Mouli

发明人： Suraj J. Mathew ,  Chandra Mouli

IPC分类号： H01L21/332 ,  H01L29/66

CPC分类号： H01L29/74

摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.

摘要翻译： 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法允许存储器阵列中的迹线布线形成在存储器件的表面上或附近。

公开(公告)号：US20130009208A1

公开(公告)日：2013-01-10

申请号：US13621002

申请日：2012-09-15

申请人： Suraj J Mathew ,  Chandra Mouli

发明人： Suraj J Mathew ,  Chandra Mouli

IPC分类号： H01L29/74

CPC分类号： H01L29/74

摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.

摘要翻译： 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法允许存储器阵列中的迹线布线形成在存储器件的表面上或附近。

公开(公告)号：US20120214285A1

公开(公告)日：2012-08-23

申请号：US13031829

申请日：2011-02-22

申请人： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

发明人： Jaydip Guha ,  Shyam Surthi ,  Suraj J. Mathew ,  Kamal M. Karda ,  Hung-Ming Tsai

IPC分类号： H01L21/336

CPC分类号： H01L21/823487 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/1104 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

摘要： Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

摘要翻译： 沟槽形成半导体材料。 遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。 电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。 这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。 在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。 内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。 导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。 栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。 公开了其他实施例。

公开(公告)号：US07005342B2

公开(公告)日：2006-02-28

申请号：US10929284

申请日：2004-08-30

申请人： Suraj J. Mathew ,  Jigish D. Trivedi

发明人： Suraj J. Mathew ,  Jigish D. Trivedi

IPC分类号： H01L21/66 ,  H01L21/425 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L27/10873

摘要： An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

公开(公告)号：US08754443B2

公开(公告)日：2014-06-17

申请号：US13621002

申请日：2012-09-15

申请人： Suraj J. Mathew ,  Chandra Mouli

发明人： Suraj J. Mathew ,  Chandra Mouli

IPC分类号： H01L29/74

CPC分类号： H01L29/74

摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.

摘要翻译： 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法允许存储器阵列中的迹线布线形成在存储器件的表面上或附近。

公开(公告)号：US20130087840A1

公开(公告)日：2013-04-11

申请号：US13269304

申请日：2011-10-07

申请人： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

发明人： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

摘要： A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

摘要翻译： 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地接近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。