公开(公告)号：US6021461A

公开(公告)日：2000-02-01

申请号：US244079

申请日：1999-02-04

申请人： Sang Hoo Dhong ,  Philip George Emma ,  William Robert Reohr ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Philip George Emma ,  William Robert Reohr ,  Joel Abraham Silberman

IPC分类号： G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0879 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02B60/1225

摘要： A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The method also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.

摘要翻译： 一种用于访问有助于增加并存储请求的高速缓冲存储器的方法，从而使应用的基地址请求通过使用内置在存储器解码电路中的内部地址生成设备来增加高速缓存的带宽。 引入内部地址生成工具简化了内置于内存系统中的典型请求者的无关控制。 该方法还可以减少利用存储器内部地址生成设备的请求所消耗的功耗。 通过在增量提取期间启用一组读出放大器，集合的联想高速缓冲存储器系统中的功耗进一步降低。

公开(公告)号：US6014036A

公开(公告)日：2000-01-11

申请号：US975368

申请日：1997-11-20

申请人： Ferenc Miklos Bozso ,  Philip George Emma ,  William Robert Reohr

发明人： Ferenc Miklos Bozso ,  Philip George Emma ,  William Robert Reohr

IPC分类号： H04L5/14 ,  H04L5/18 ,  H04L25/02 ,  H03K19/0175

CPC分类号： H04L5/18 ,  H04L5/1476

摘要： A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes circuitry for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing device for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

摘要翻译： 用于双向交换数据的电路包括通过总线电连接在其间的多个实体，用于彼此发送和接收数据的多个实体。 至少一个交换电路在多个实体之间的连接点处电连接到总线。 所述至少一个交换电路包括用于在发送数据模式和接收数据模式之间定时数据传输以及在各个模式期间发送和接收数据的电路。 所述至少一个交换电路包括路由设备，用于从所述多个实体同时接收数据，然后同时向所述多个实体发送数据而不冲突数据。

公开(公告)号：US5955781A

公开(公告)日：1999-09-21

申请号：US6575

申请日：1998-01-13

申请人： Rajiv Vasant Joshi ,  William Robert Reohr

发明人： Rajiv Vasant Joshi ,  William Robert Reohr

IPC分类号： H01L23/36 ,  H01L21/822 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L27/04 ,  H01L27/12 ,  H05K7/20 ,  H01L23/34

CPC分类号： H01L23/522 ,  H01L23/3677 ,  H01L23/3732 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10158

摘要： A semiconductor chip structure includes a substrate, at least one thermal conductor embedded within the semiconductor chip structure, the thermal conductor providing electrical insulation and a plurality of devices formed within the structure adjacent to the at least one thermal conductor such that during operation heat produced in the devices is transferred into and through the at least one thermal conductor to reduce an operating temperature of the devices. This structure is particularly useful in silicon-on insulator devices. A method of forming embedded thermal conductors in a semiconductor chip includes the steps of providing a substrate having an oxide layer formed thereon, etching trenches into the oxide layer, depositing diamond to fill the trenches to form thermal conductors contacting the substrate and forming devices and contacts adjacent to the thermal conductors for providing heat flow paths to reduce an operating temperature of the devices.

公开(公告)号：US20240212733A1

公开(公告)日：2024-06-27

申请号：US18478140

申请日：2023-09-29

申请人： William Robert Reohr

发明人： William Robert Reohr

IPC分类号： G11C11/16 ,  G11C11/44

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/44

摘要： A write circuit for an MJJ-based memory circuit includes first and second current sources configured to generate first and second currents, respectively. The first current imparting an easy axis magnetic field component on an MJJ in a selected memory cell during a write operation. The second current inducing a third current in the selected memory cell that passes through the MJJ, the third current being a seed current for setting a π-state current of the MJJ in a superconducting loop of the selected memory cell. The first current source is configured such that, during the write operation, the MJJ cell transitions: (i) from a π-state, in which a clockwise or counter-clockwise current circulates in the superconducting loop, to a zero-state, in which no current circulates in the superconducting loop, back to the π-state; or (ii) from the zero-state to the π-state; or (iii) from the π-state to the zero-state.

公开(公告)号：US09595970B1

公开(公告)日：2017-03-14

申请号：US15079106

申请日：2016-03-24

申请人： William Robert Reohr ,  Robert J Voigt

发明人： William Robert Reohr ,  Robert J Voigt

IPC分类号： H03K19/195 ,  H03K19/00 ,  H03K19/177 ,  G11C11/44 ,  G06N99/00

CPC分类号： H03K19/195 ,  G06N99/002 ,  G11C5/025 ,  G11C11/44 ,  H03K19/0008 ,  H03K19/1776

摘要： One embodiment describes a superconducting cell array logic circuit system. The system includes a plurality of superconducting cells arranged in an array of at least one row and at least one column. The superconducting cell array logic circuit system can be configured to implement a logic operation on at least one logic input signal received at at least one respective input associated with the respective at least one row to provide at least one logic output signal on at least one respective output associated with the at least one column based on a predetermined selective coupling of the at least one input to the at least one output via the plurality of superconducting cells.

摘要翻译： 一个实施例描述了超导单元阵列逻辑电路系统。 该系统包括布置成至少一行和至少一列的阵列的多个超导单元。 超导单元阵列逻辑电路系统可以被配置为对在与相应的至少一行相关联的至少一个相应输入处接收的至少一个逻辑输入信号实施逻辑运算，以在至少一个相应的至少一个相应的逻辑输入信号上提供至少一个逻辑输出信号 基于经由多个超导单元的至少一个输入到所述至少一个输出的预定选择性耦合，与所述至少一个列相关联的输出。

公开(公告)号：US09520181B1

公开(公告)日：2016-12-13

申请号：US14854994

申请日：2015-09-15

申请人： Donald L. Miller ,  Andrew Hostetler Miklich ,  Anna Y. Herr ,  Quentin P. Herr ,  William Robert Reohr

发明人： Donald L. Miller ,  Andrew Hostetler Miklich ,  Anna Y. Herr ,  Quentin P. Herr ,  William Robert Reohr

IPC分类号： G11C11/44 ,  G11C11/16

CPC分类号： G11C11/44 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675

摘要： One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.

摘要翻译： 一个实施例描述了JMRAM存储器单元系统。 该系统包括相位滞后磁约瑟夫逊结（PHMJJ），其响应于在数据写入操作期间提供的写入电流而存储第一二进制状态和第二二进制状态之一，并且基于所存储的数字状态提供超导相位。 该系统还包括定向写入元件，其被配置为在数据写入操作期间提供方向偏置电流，以在对应于第一二进制状态的预定方向上提供PHMJJ的超导相位。 该系统还包括至少一个约瑟夫逊结，其具有基于PHMJJ的超导相位的临界电流，并且被配置为响应于在读取操作期间提供的读取电流来提供对应于存储的数字状态的输出。

公开(公告)号：US20130229189A1

公开(公告)日：2013-09-05

申请号：US13411068

申请日：2012-03-02

申请人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

发明人： Liang-Teck Pang ,  William Robert Reohr ,  Phillip John Restle

IPC分类号： G01R31/14

CPC分类号： G01R31/3008

摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.

摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。

公开(公告)号：US07158604B1

公开(公告)日：2007-01-02

申请号：US09086237

申请日：1998-05-28

申请人： Philip George Emma ,  Rajiv Vasant Joshi ,  William Robert Reohr

发明人： Philip George Emma ,  Rajiv Vasant Joshi ,  William Robert Reohr

IPC分类号： H04L23/00

CPC分类号： H04L5/20

摘要： A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

摘要翻译： 用于在存储器系统中将二进制信号上的差分信号叠加的系统和方法。 该技术可以在公共汽车和多种存储介质中执行。 取决于要被容忍的噪声，并且取决于编码装置的复杂性，可以以多种方式实现。

公开(公告)号：US06744087B2

公开(公告)日：2004-06-01

申请号：US10256881

申请日：2002-09-27

申请人： James A. Misewich ,  William Robert Reohr ,  Alejandro Gabriel Schrott ,  Li-Kong Wang

发明人： James A. Misewich ,  William Robert Reohr ,  Alejandro Gabriel Schrott ,  Li-Kong Wang

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.

摘要翻译： 垂直铁电栅极场效应晶体管（FeGFET）器件包括形成在衬底的上表面上的衬底和第一漏极/源极。 在第一漏/源电极的上表面上形成导电沟道区，并与第一漏/源电极电接触。 FeGFET器件还包括形成在通道区域的至少一个侧壁上的铁电栅极区域，与铁电栅极区域电接触的至少一个栅极电极和形成在沟道区域的上表面上的第二漏极/源极电极，以及 电接触通道区域。 铁电栅极区域响应于施加在栅极电极和第一和第二漏极/源极电极中的至少一个之间的电位而选择性地极化。 可以形成包括多个FeGFET装置的非易失性存储器阵列。

公开(公告)号：US06515515B1

公开(公告)日：2003-02-04

申请号：US09468188

申请日：1999-12-21

申请人： Ferenc Miklos Bozso ,  Philip George Emma ,  William Robert Reohr

发明人： Ferenc Miklos Bozso ,  Philip George Emma ,  William Robert Reohr

IPC分类号： H03K19094

CPC分类号： H04L5/18 ,  H04L5/1476

摘要： A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

摘要翻译： 用于双向交换数据的电路包括通过总线电连接在其间的多个实体，用于彼此发送和接收数据的多个实体。 至少一个交换电路在多个实体之间的连接点处电连接到总线。 所述至少一个交换电路包括用于在发送数据模式和接收数据模式之间定时数据传送以及在各个模式期间发送和接收数据的装置。 所述至少一个交换电路包括路由装置，用于从所述多个实体同时接收数据，然后同时向所述多个实体发送数据而不冲突数据。