公开(公告)号：US08887171B2

公开(公告)日：2014-11-11

申请号：US12647671

申请日：2009-12-28

申请人： Justin J. Song ,  John H. Crawford

发明人： Justin J. Song ,  John H. Crawford

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F9/5094 ,  Y02D10/22

摘要： An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough—inefficient patterns are instead predicted to be resident for longer—then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined. Upon receipt of a request for a core to enter a power state, a power management unit may select either the hardware predicted power state, if the accuracy is high enough, or utilize the requested power state, if the accuracy of the hardware prediction is not high enough.

摘要翻译： 这里描述了一种用于避免低效的核心跳跃并提供硬件辅助电源状态选择的装置和方法。 预测未来的核心空闲活动。 如果预期高效核心跳情景的活动模式的居住地位足够大，则确定核心是有效的并被允许的。 然而，如果高效的活动模式不被预测为居民，因为足够长时间而不是预期为较长时间驻留，则核心跳跃请求被拒绝。 因此，设计人员可以实施一种策略，以避免核心跳跃的权重，核心跳跃的权重可能会降低核心跳跃条件的潜在收益，而不考虑执行核心跳的惩罚，例如核心跳的时间损失 。 另外，与硬件的硬件电源状态相关联的空闲持续时间可以在硬件中预测。 此外，确定空闲持续时间预测的精度。 在接收到核心进入电源状态的请求时，如果硬件预测的准确度不是，功率管理单元可以选择硬件预测功率状态，如果精度足够高，或者利用所请求的功率状态 足够高。

公开(公告)号：US20140189403A1

公开(公告)日：2014-07-03

申请号：US13730074

申请日：2012-12-28

申请人： Eugene Gorbatov ,  Paul S. Diefenbaugh ,  John H. Crawford ,  Anil K. Kumar ,  Richard J. Greco

发明人： Eugene Gorbatov ,  Paul S. Diefenbaugh ,  John H. Crawford ,  Anil K. Kumar ,  Richard J. Greco

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3228 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.

摘要翻译： 方法和系统可以提供用于确定与平台相关联的等待时间约束，并且基于等待时间约束来确定空闲窗口。 此外，可以指示平台上的多个设备在空闲窗口期间停止一个或多个活动。 在一个示例中，平台在空闲窗口期间处于睡眠状态。

公开(公告)号：US20130275995A1

公开(公告)日：2013-10-17

申请号：US13912777

申请日：2013-06-07

申请人： Sailesh Kottapalli ,  John H. Crawford

发明人： Sailesh Kottapalli ,  John H. Crawford

IPC分类号： G06F9/52

CPC分类号： G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

摘要： In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US08473963B2

公开(公告)日：2013-06-25

申请号：US13069684

申请日：2011-03-23

申请人： Sailesh Kottapalli ,  John H. Crawford

发明人： Sailesh Kottapalli ,  John H. Crawford

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F7/38 ,  G06F13/00

CPC分类号： G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

摘要： In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US07383468B2

公开(公告)日：2008-06-03

申请号：US10634899

申请日：2003-08-06

申请人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

发明人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

IPC分类号： G06F11/00

CPC分类号： G06F11/073 ,  G06F11/0751 ,  G06F11/1064 ,  G06F12/1036

摘要： The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

摘要翻译： 本发明涉及高度可靠的微处理器的设计，更具体地涉及使用周期性地检查关键处理器资源的有效性的专用状态机。 在本发明的实施例中，检测存储在处理器资源中的信息中的错误的装置包括：错误检测部件，被配置为控制对存储在处理器资源中的信息中的错误的检测; 以及耦合到所述错误检测组件的比较组件，其被配置为从所述处理器资源接收所述信息并从所述检测组件输入。 所述比较部件还被配置为确定所述信息是否有效，并且如果所述信息是无效的，则输出信号以替换所述信息。

公开(公告)号：US07010671B2

公开(公告)日：2006-03-07

申请号：US10094498

申请日：2002-03-07

申请人： John H. Crawford ,  Donald Alpert

发明人： John H. Crawford ,  Donald Alpert

IPC分类号： G06F9/48 ,  G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/45533

摘要： A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

摘要翻译： 本文公开了一种计算机系统，其包括专门设计为在虚拟操作模式下操作的给定微处理器，其允许先前为先前设计的单个程序微处理器写入的软件程序在受特定设计的主机之下的受保护的，分页的多任务环境中执行 操作软件程序。 该系统还包括使用形成主机程序的一部分的仿真软件来执行软件中断（INTn）指令的装置，以便模拟这些指令将由较早的微处理器执行的方式。 作为对整个计算机系统的独特改进，INTn指令中的某些指令通过仿真软件执行，而其他指令则通过与给定的微处理器及其主机操作软件程序协作的先前编写的程序来执行。

公开(公告)号：US06385718B1

公开(公告)日：2002-05-07

申请号：US08919570

申请日：1997-08-29

申请人： John H. Crawford ,  Donald Alpert

发明人： John H. Crawford ,  Donald Alpert

IPC分类号： G06F944

CPC分类号： G06F9/4812 ,  G06F9/45533

摘要： A computer system including a given microprocessor specifically designed to operate in a virtual operating mode allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

摘要翻译： 包括专门设计为以虚拟操作模式操作的给定微处理器的计算机系统允许先前为先前设计的单个程序微处理器写入的软件程序在特别设计的主机操作软件程序下的受保护的分页的多任务环境中执行。 该系统还包括使用形成主机程序的一部分的仿真软件来执行软件中断（INTn）指令的装置，以便模拟这些指令将由较早的微处理器执行的方式。 作为对整个计算机系统的独特改进，INTn指令中的某些指令通过仿真软件执行，而其他指令则通过与给定的微处理器及其主机操作软件程序协作的先前编写的程序来执行。

公开(公告)号：US6163764A

公开(公告)日：2000-12-19

申请号：US170131

申请日：1998-10-12

申请人： Carole Dulong ,  John H. Crawford

发明人： Carole Dulong ,  John H. Crawford

IPC分类号： G06F9/30 ,  G06F9/455

CPC分类号： G06F9/30189 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/45504

摘要： A method and apparatus for emulating an instruction on a processor. The instruction operates on an operand in a first data format and the processor operates in a second data format. The operand is converted from the first data format to the second data format. The processor then executes the instruction in the second data format to generate a result in the second data format. The result is converted from the second data format to the first data format.

摘要翻译： 一种用于在处理器上仿真指令的方法和装置。 指令以第一数据格式的操作数进行操作，并且处理器以第二数据格式进行操作。 操作数从第一个数据格式转换成第二个数据格式。 然后处理器以第二数据格式执行指令，以产生第二数据格式的结果。 结果从第二数据格式转换为第一数据格式。

公开(公告)号：US5948099A

公开(公告)日：1999-09-07

申请号：US744818

申请日：1991-08-12

申请人： John H. Crawford ,  Mustafiz R. Choudhury

发明人： John H. Crawford ,  Mustafiz R. Choudhury

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/30 ,  G06F9/455 ,  G06F12/04 ,  G06F9/315

CPC分类号： G06F7/768 ,  G06F9/30025

摘要： A microprocessor instruction for performing an in-place byte swap on 32-bit data type to convert data stored in a big-endian memory format to a little-endian memory format, or visa-versa, is described. The invention comprises a modified barrel shifter which includes a plurality of multiplexers for selectively coupling data from one or more input buses to an output bus. The coupling of the individual bit lines of the data buses is arranged such that the lower order bits of the 32-bit quantity are exchanged with the higher order bits and visa-versa. Control lines connected to each of the multiplexers provide a means for controlling the byte swapping operation.

摘要翻译： 描述了一种用于在32位数据类型上执行就地字节交换以将以大端存储器格式存储的数据转换为小端存储器格式或反之亦然的微处理器指令。 本发明包括一种改进的桶形移位器，其包括用于选择性地将来自一个或多个输入总线的数据耦合到输出总线的多路复用器。 数据总线的各个位线的耦合被布置成使得32位数量的较低位与高阶比特交换，反之亦然。 连接到每个多路复用器的控制线提供用于控制字节交换操作的装置。

公开(公告)号：US5201043A

公开(公告)日：1993-04-06

申请号：US897596

申请日：1992-06-10

申请人： John H. Crawford ,  Ashish B. Dixit

发明人： John H. Crawford ,  Ashish B. Dixit

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/36

CPC分类号： G06F11/0763 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3648

摘要： A microprocessor which includes means for detecting misaligned data reference is described. The detecting means is selectable such that when it is enabled and reference is made to a misaligned data object, a fault is produced which interrupts the currently executing program. The detecting means comprises two mode bits stored within the microprocessor. The first mode bit provides control of the fault at the least privileged level of execution (i.e., the applications level) while the second mode bit provides control of the fault at the most privileged level (i.e., the operating system level). Both mode bits must be set to "1" in order for the detecting means to be enabled. The use of two separate mode bits for optionally enabling alignment checking provides optimum programming flexibility.

摘要翻译： 描述了包括用于检测未对准数据参考的装置的微处理器。 检测装置是可选择的，使得当它被启用并被引用到未对准的数据对象时，产生中断当前正在执行的程序的故障。 检测装置包括存储在微处理器内的两个模式位。 第一模式位在至少特权级别的执行级别（即，应用级别）提供对故障的控制，而第二模式位提供对最高特权级别（即，操作系统级别）的故障的控制。 为了启用检测装置，两个模式位必须设置为“1”。 使用两个单独的模式位可选地实现对准检查提供了最佳的编程灵活性。