公开(公告)号：US08799583B2

公开(公告)日：2014-08-05

申请号：US12786787

申请日：2010-05-25

申请人： Mark S. Farrell ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Mark S. Farrell ,  Jonathan T. Hsieh ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3834 ,  G06F9/528 ,  G06F12/0815 ,  G06F2212/62

摘要： A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.

摘要翻译： 一种通过一系列存储器访问操作支持共享数据的原子访问的方法和中央处理单元。 处理器状态标志被复位。 在处理器状态标志的设置之后，处理器执行具有访问包含在其本地高速缓存中的共享数据的子集的指令的程序指令序列。 在程序指令序列的执行期间，并且响应于另一个处理器对共享数据子集的修改，处理器状态标志被置位。 在执行程序指令序列之后，并且基于处理器状态标志的状态，执行第一程序处理或第二程序处理。 在一些示例中，第一程序处理包括将结果数据存储到本地高速缓存中，并且第二程序处理包括丢弃结果数据。

公开(公告)号：US08688661B2

公开(公告)日：2014-04-01

申请号：US13524921

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： G06F9/467 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834

摘要： A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

摘要翻译： 交易通过交易开始指令启动。 交易执行期间，交易可能会中止。 如果交易中止，则确定交易的类型。 基于事务是第一种类型的事务，在事务开始指令中恢复执行，并且基于事务是第二类型，在事务开始指令之后的指令处恢复执行。 不管交易类型如何，恢复执行包括恢复在事务开始指令中指定的一个或多个寄存器，并丢弃事务存储。 对于一种类型的事务，非约束事务，恢复包括将信息存储在事务诊断块中。

公开(公告)号：US20130339702A1

公开(公告)日：2013-12-19

申请号：US13524839

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Timothy J. Slegel

IPC分类号： G06F9/38

CPC分类号： G06F9/3865 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/466 ,  G06F9/4812

摘要： Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

公开(公告)号：US20130339691A1

公开(公告)日：2013-12-19

申请号：US13517779

申请日：2012-06-14

申请人： James J. Bonanno ,  Marcel Mitran ,  Brian R. Prasky ,  Joran Siu ,  Timothy J. Slegel ,  Alexander Vasilevskiy

发明人： James J. Bonanno ,  Marcel Mitran ,  Brian R. Prasky ,  Joran Siu ,  Timothy J. Slegel ,  Alexander Vasilevskiy

IPC分类号： G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3806 ,  G06F9/3844

摘要： Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.

摘要翻译： 实施例涉及分支预测预加载。 一方面包括用于分支预测预加载的系统。 该系统包括耦合到处理电路的指令高速缓存和分支目标缓冲器（BTB），所述处理电路被配置为执行方法。 该方法包括从指令高速缓冲存储器中取出指令流中的多个指令，以及对指令流中的分支预测预加载指令进行解码。 基于分支预测预加载指令来确定预测转移指令的地址。 基于分支预测预加载指令来确定预测目标地址。 在分支预测预加载指令中识别掩码字段，并且基于掩码字段来确定分支指令长度。 基于执行分支预测预加载指令，BTB预先加载预测分支指令的地址，分支指令长度，分支类型和预测目标地址。

公开(公告)号：US20130339561A1

公开(公告)日：2013-12-19

申请号：US13524903

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Damian L. Osisek ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Damian L. Osisek ,  Timothy J. Slegel

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/466 ,  G06F11/3636

摘要： A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.

公开(公告)号：US20130339329A1

公开(公告)日：2013-12-19

申请号：US13524921

申请日：2012-06-15

申请人： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Christian Jacobi ,  Timothy J. Slegel

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F9/467 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834

摘要： A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

公开(公告)号：US08417916B2

公开(公告)日：2013-04-09

申请号：US11972725

申请日：2008-01-11

申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

IPC分类号： G06F12/08

CPC分类号： G06F12/1475 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30145 ,  G06F12/10

摘要： What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

摘要翻译： 公开的是针对计算机系统的机器结构定义的集合关键和清晰的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的机器指令。 从第一通用寄存器获得的是指示存储帧是小块还是大块数据的帧大小字段。 从第二通用寄存器获得的是要执行指令的存储帧的操作数地址。 如果存储帧是小块，则仅在小块上执行指令。 如果指示的存储帧是大数据块，则从第二通用寄存器获得大数据块内的初始第一数据块的操作数地址。 在从初始第一块开始的所有块上执行帧管理指令。

公开(公告)号：US20120166758A1

公开(公告)日：2012-06-28

申请号：US13412889

申请日：2012-03-06

申请人： Dan F. Greiner ,  Charles W Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

发明人： Dan F. Greiner ,  Charles W Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

IPC分类号： G06F12/10

CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

公开(公告)号：US20120137106A1

公开(公告)日：2012-05-31

申请号：US13336106

申请日：2011-12-23

申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/1027

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用了转换表条目中包含的格式控制字段，则表项包含大小至少为1M字节的大块数据的帧地址。 然后将帧地址与虚拟地址的偏移部分组合以形成主存储器或存储器中的小4K字节数据块的转换地址。

公开(公告)号：US20120137073A1

公开(公告)日：2012-05-31

申请号：US13368363

申请日：2012-02-08

申请人： Dan F. Greiner ,  Timothy J. Slegel

发明人： Dan F. Greiner ,  Timothy J. Slegel

IPC分类号： G06F13/00 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30047 ,  G06F9/30058 ,  G06F9/30167 ,  G06F9/322

摘要： A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

摘要翻译： 一种用于指定目标缓存高速缓存级别和感兴趣的目标高速缓存属性的用于获得一个或多个目标高速缓存的高速缓存属性的计算机体系结构的设施和缓存机器指令。 所请求的高速缓存属性被保存在一个寄存器中。