利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

35 条记录 (耗时 0.021 秒)

    BARRIERLESS SINGLE-PHASE INTERCONNECT
    32.
    发明申请
    BARRIERLESS SINGLE-PHASE INTERCONNECT 审中-公开
    无障碍单相互连

    公开(公告)号：US20120153483A1

    公开(公告)日：2012-06-21

    申请号：US12973281

    申请日：2010-12-20

    申请人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

    发明人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53261 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.

    摘要翻译： 形成互连结构的方法和包括所述互连结构的集成电路。 该方法包括：在导电层上沉积介电层; 在所述电介质层中形成开口以暴露所述导电层; 形成包含熔点在铜的熔点和钨的熔点之间的金属或化合物的无障碍单相互连。 形成包括在开口内和介电层的上表面上沉积一层金属或化合物。优选地，无障碍单相互连包括钴或含钴化合物。 因此，包括通孔和相关线路的互连结构由单相金属或化合物构成，而不需要在互连和下面的电介质之间使用不同的材料，从而改善电性能和可靠性并进一步简化互连 形成过程。

    Method of fabricating a carbon nanotube interconnect structures
    33.
    发明授权
    Method of fabricating a carbon nanotube interconnect structures 有权
    制造碳纳米管互连结构的方法

    公开(公告)号：US07625817B2

    公开(公告)日：2009-12-01

    申请号：US11325774

    申请日：2005-12-30

    申请人： Florian Gstrein ,  Valery M. Dubin ,  Juan E. Dominguez ,  Adrien R. Lavoie

    发明人： Florian Gstrein ,  Valery M. Dubin ,  Juan E. Dominguez ,  Adrien R. Lavoie

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/75 ,  H01L2924/00

    摘要： A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.

    摘要翻译： 一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。 一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。 一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。

    COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS
    34.
    发明申请
    COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS 审中-公开
    铜金属化使用金属内衬使用反射

    公开(公告)号：US20090169760A1

    公开(公告)日：2009-07-02

    申请号：US11968136

    申请日：2007-12-31

    申请人： Rohan Akolkar ,  Florian Gstrein ,  Boyan Boyanov ,  Sridhar Balakrishnan

    发明人： Rohan Akolkar ,  Florian Gstrein ,  Boyan Boyanov ,  Sridhar Balakrishnan

    IPC分类号： C23C4/06 ,  B05D5/12

    CPC分类号： C23C14/046 ,  C23C14/025 ,  C23C14/16 ,  C23C14/5806 ,  C23C14/588 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/53238

    摘要： Methods for making copper (Cu) interconnects in semiconductor devices for interconnect dimensions less than 50 nm are described. The processes form Cu interconnects using a sequence of barrier layer, liner layer, and Cu deposition layer depositions, followed by a thermally assisted Cu reflow of the Cu deposition layer, and then a chemical mechanical polish (CMP) to removed excess portions of the reflowed Cu. The liner layer comprises noble metals such as Ru, Ir, Os, Rh, Re, Pd, Pt, and Au. Such processes avoids the formation of voids in copper interconnects with dimensions less than 50 nm.

    摘要翻译： 描述了半导体器件中铜（Cu）互连的互连尺寸小于50nm的方法。 这些过程使用阻挡层，衬层和Cu沉积层沉积序列形成Cu互连，随后是Cu沉积层的热辅助铜回流，然后用化学机械抛光（CMP）去除被回流的多余部分 铜。 衬里层包括贵金属如Ru，Ir，Os，Rh，Re，Pd，Pt和Au。 这种方法避免了在尺寸小于50nm的铜互连件中形成空隙。