摘要:
Methods for making copper (Cu) interconnects in semiconductor devices for interconnect dimensions less than 50 nm are described. The processes form Cu interconnects using a sequence of barrier layer, liner layer, and Cu deposition layer depositions, followed by a thermally assisted Cu reflow of the Cu deposition layer, and then a chemical mechanical polish (CMP) to removed excess portions of the reflowed Cu. The liner layer comprises noble metals such as Ru, Ir, Os, Rh, Re, Pd, Pt, and Au. Such processes avoids the formation of voids in copper interconnects with dimensions less than 50 nm.
摘要:
Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a doping material on an overburden region of a conductive structure, diffusing a portion of the doping material into a portion of the conductive structure, and then removing the overburden region.
摘要:
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要:
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a metallization structure for an integrated circuit involves forming an exposed surface above a substrate, the exposed surface including regions of exposed dielectric material and regions of exposed metal. The method also involves forming, using a selective metal deposition process, a metal layer on the regions of exposed metal without forming the metal layer on the regions of exposed dielectric material.
摘要:
Embodiments of the present disclosure are directed towards metallization of a fluorocarbon-based dielectric material for interconnect applications. In one embodiment, an apparatus includes a semiconductor substrate, a device layer disposed on the semiconductor substrate, the device layer including one or more transistor devices, and an interconnect layer disposed on the device layer, the interconnect layer comprising a fluorocarbon-based dielectric material, where x represents a stoichiometric quantity of fluorine relative to carbon in the dielectric material, and one or more interconnect structures configured to route electrical signals to or from the one or more transistor devices, the one or more interconnect structures comprising cobalt (Co), or ruthenium (Ru), or combinations thereof. Other embodiments may be described and/or claimed.
摘要:
A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.
摘要:
A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.
摘要:
A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
摘要:
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
摘要:
Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described.