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    BARRIERLESS SINGLE-PHASE INTERCONNECT
    1.
    发明申请
    BARRIERLESS SINGLE-PHASE INTERCONNECT 审中-公开
    无障碍单相互连

    公开(公告)号：US20120153483A1

    公开(公告)日：2012-06-21

    申请号：US12973281

    申请日：2010-12-20

    申请人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

    发明人： Rohan N. Akolkar ,  Florian Gstrein ,  Daniel J. Zierath

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53261 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.

    摘要翻译： 形成互连结构的方法和包括所述互连结构的集成电路。 该方法包括：在导电层上沉积介电层; 在所述电介质层中形成开口以暴露所述导电层; 形成包含熔点在铜的熔点和钨的熔点之间的金属或化合物的无障碍单相互连。 形成包括在开口内和介电层的上表面上沉积一层金属或化合物。优选地，无障碍单相互连包括钴或含钴化合物。 因此，包括通孔和相关线路的互连结构由单相金属或化合物构成，而不需要在互连和下面的电介质之间使用不同的材料，从而改善电性能和可靠性并进一步简化互连 形成过程。

    Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics
    3.
    发明申请
    Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics 审中-公开
    氟化低K电介质的自形成金属氟化物屏障

    公开(公告)号：US20100244252A1

    公开(公告)日：2010-09-30

    申请号：US12416131

    申请日：2009-03-31

    申请人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    发明人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    IPC分类号： H01L23/538 ,  H01L21/768

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76867 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.

    摘要翻译： 公开了在氟化低K电介质和Cu或Cu合金互连的界面处形成氟化物金属屏障的装置和方法。 氟化物金属屏障可以防止互连与氟化低K电介质反应。 该方法可以包括在氟化低K电介质上沉积金属或金属合金薄膜。 薄膜可以包括与来自氟化低K电介质的游离氟和/或氟化合物反应以形成氟化物金属屏障的金属或金属合金元素。

    Liner layers for metal interconnects
    4.
    发明授权
    Liner layers for metal interconnects 有权
    用于金属互连的衬里层

    公开(公告)号：US08779589B2

    公开(公告)日：2014-07-15

    申请号：US12973773

    申请日：2010-12-20

    申请人： Harsono S. Simka ,  Daniel J. Zierath ,  Michael G. Haverty ,  Sadasivan Shankar

    发明人： Harsono S. Simka ,  Daniel J. Zierath ,  Michael G. Haverty ,  Sadasivan Shankar

    IPC分类号： H01L23/52 ,  H01L21/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

    摘要翻译： 提供了用于集成电路的电互连和制造互连的方法。 提供了包括铜互连件的装置，其具有包含银和第二成分（诸如镧，钛，钨，锆，锑或钙）的金属衬里层。 方法包括提供具有在其中形成的沟槽或通孔的衬底，在特征的表面上形成银合金层，其包含银和选自镧，钛，钨，锆，锑和钙的第二组分， 沉积铜种子层，并将铜沉积到特征中。

    ELECTROLESS FILLED CONDUCTIVE STRUCTURES
    7.
    发明申请
    ELECTROLESS FILLED CONDUCTIVE STRUCTURES 有权
    电镀填充导电结构

    公开(公告)号：US20130270703A1

    公开(公告)日：2013-10-17

    申请号：US13976084

    申请日：2011-12-21

    申请人： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

    发明人： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

    IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/538

    CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

    摘要翻译： 公开了能够通过无电解材料沉积技术形成的互连，通孔，金属栅极和其它导电特征的技术。 在一些实施方案中，该技术采用无电填料结合无电成核材料（ENM）和无电压抑制材料（ESM）之间的高生长速率选择性，以产生这些特征的自下而上或其他期望的填充图案。 合适的ENM可能存在于底层或其他现有结构中，或可提供。 提供ESM以防止或以其他方式阻止特征的ESM覆盖区域的成核，这又防止或以其他方式减缓这些区域上的无电生长速率。 因此，ENM场地的无电增长率高于ESM站点上的无电增长率。

    Modified electroplating solution components in a low-acid electrolyte solution
    8.
    发明授权
    Modified electroplating solution components in a low-acid electrolyte solution 有权
    改性电镀溶液成分在低酸电解液中

    公开(公告)号：US07371311B2

    公开(公告)日：2008-05-13

    申请号：US10682276

    申请日：2003-10-08

    申请人： Daniel J Zierath ,  Vinay Chikarmane ,  Valery M Dubin

    发明人： Daniel J Zierath ,  Vinay Chikarmane ,  Valery M Dubin

    IPC分类号： C25D3/38 ,  C25D21/18

    CPC分类号： C25D21/12

    摘要： An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

    摘要翻译： 本发明的一个实施方案提供了一种通过改变低酸性电镀溶液的组分浓度来减小模内厚度变化的方法。 对于一个实施例，调平器浓度被充分增加以将模具厚度变化减小到指定值。 对于本发明的一个实施例，矫直机和抑制器增加以减小模内厚度变化并且基本上减少多个电镀缺陷。 在这样的实施例中，确定矫直机和抑制器的组合浓度以保持足够的间隙填充。

    Electroless filled conductive structures
    9.
    发明授权
    Electroless filled conductive structures 有权
    无电解填充导电结构

    公开(公告)号：US09123706B2

    公开(公告)日：2015-09-01

    申请号：US13976084

    申请日：2011-12-21

    申请人： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

    发明人： Daniel J. Zierath ,  Shaestagir Chowdhury ,  Chi-Hwa Tsang

    IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/538 ,  H01L23/532

    CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

    摘要翻译： 公开了能够通过无电解材料沉积技术形成的互连，通孔，金属栅极和其它导电特征的技术。 在一些实施方案中，该技术采用无电填料结合无电成核材料（ENM）和无电压抑制材料（ESM）之间的高生长速率选择性，以产生这些特征的自下而上或其他期望的填充图案。 合适的ENM可能存在于底层或其他现有结构中，或可提供。 ESM的设置是为了防止或以其他方式抑制ESM覆盖的特征区域的成核，这又防止或以其他方式减缓这些区域的无电生长速率。 因此，ENM场地的无电增长率高于ESM站点上的无电增长率。

    SELF FORMING METAL FLUORIDE BARRIERS FOR FLUORINATED LOW-K DIELECTRICS
    10.
    发明申请
    SELF FORMING METAL FLUORIDE BARRIERS FOR FLUORINATED LOW-K DIELECTRICS 审中-公开
    用于氟化低K电介质的自制金属氟化物阻挡层

    公开(公告)号：US20120258588A1

    公开(公告)日：2012-10-11

    申请号：US13529067

    申请日：2012-06-21

    申请人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    发明人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    IPC分类号： H01L21/768

    CPC分类号： B67D7/348 ,  G07F13/025

    摘要： A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.

    摘要翻译： 公开了在氟化低K电介质和Cu或Cu合金互连的界面处形成氟化物金属屏障的装置和方法。 氟化物金属屏障可以防止互连与氟化低K电介质反应。 该方法可以包括在氟化低K电介质上沉积金属或金属合金薄膜。 薄膜可以包括与来自氟化低K电介质的游离氟和/或氟化合物反应以形成氟化物金属屏障的金属或金属合金元素。