公开(公告)号：US07633102B2

公开(公告)日：2009-12-15

申请号：US11866072

申请日：2007-10-02

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L27/088

CPC分类号： H01L29/7811 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

摘要翻译： 通过沟槽底部的掺杂剂注入将低功率沟槽MOSFET器件中的漂移区域合并在一起可以使用非常小的单元间距，导致非常高的沟道密度和均匀掺杂的沟道，从而显着降低 渠道阻力。 通过适当选择植入剂量和漂移区域的退火参数，可以严密控制器件的沟道长度，并且可以使沟道掺杂高度均匀。 与常规器件相比，阈值电压降低，沟道电阻降低，并且漂移区导通电阻也降低。 实施合并的漂移区域需要并入新的边缘终端设计，使得由P外延层和N +基底形成的PN结可以在模具的边缘终止。

公开(公告)号：US20080211014A1

公开(公告)日：2008-09-04

申请号：US11930686

申请日：2007-10-31

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

摘要翻译： 功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。 在衬底上有相同掺杂的更轻掺杂的外延层。 外延层上方是由相反型掺杂形成的阱区。 覆盖阱是重掺杂的第一导电类型的上源层。 沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。 沟槽的底部填充有掺杂多晶硅屏蔽层。 诸如氮化硅的层间电介质覆盖屏蔽。 栅极区域由另一层掺杂多晶硅形成。 第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。 在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

公开(公告)号：US20080121989A1

公开(公告)日：2008-05-29

申请号：US11930371

申请日：2007-10-31

申请人： Christopher B. Kocon ,  Jun Zeng

发明人： Christopher B. Kocon ,  Jun Zeng

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

摘要： An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

摘要翻译： 改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。 上层还在其上表面包括具有与身体区域相反的第二极性的多个重掺杂源区。 栅极沟槽从上层的上表面延伸到漏极区，并且将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽被填充到具有导电栅极材料的选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面 的设备。

公开(公告)号：US20080023759A1

公开(公告)日：2008-01-31

申请号：US11866072

申请日：2007-10-02

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

摘要翻译： 通过沟槽底部的掺杂剂注入将低功率沟槽MOSFET器件中的漂移区域合并在一起可以使用非常小的单元间距，导致非常高的沟道密度和均匀掺杂的沟道，从而显着降低 渠道阻力。 通过适当选择植入剂量和漂移区域的退火参数，可以严密控制器件的沟道长度，并且可以使沟道掺杂高度均匀。 与常规器件相比，阈值电压降低，沟道电阻降低，并且漂移区导通电阻也降低。 实现合并的漂移区域需要并入新的边缘终端设计，使得由P外延层和N + +衬底形成的PN结可以在晶片的边缘端接。

公开(公告)号：US06921939B2

公开(公告)日：2005-07-26

申请号：US09844347

申请日：2001-04-27

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

摘要翻译： 制造功率MOSFET的方法包括在半导体层中形成沟槽，形成衬底沟槽的栅极电介质层，在沟槽的下部形成栅极导电层，形成电介质层以填充该沟槽的上部 沟。 去除与电介质层横向相邻的半导体层的部分，使得其上部从半导体层向外延伸。 间隔件横向邻近介质层的向外延伸的上部形成，间隔件用作用于限定源/体接触区域的自对准掩模。

公开(公告)号：US06759719B2

公开(公告)日：2004-07-06

申请号：US10327443

申请日：2002-12-20

申请人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

发明人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

IPC分类号： H01L2976

CPC分类号： H01L29/0615 ,  H01L29/1608 ,  H01L29/267 ,  Y10S438/931

摘要： A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.

摘要翻译： 硅半导体管芯包括重掺杂硅衬底以及设置在衬底上的包含第一导电类型的掺杂硅的上层。 上层包括邻近边缘终止区的第二相反导电类型的阱区，其包括具有比硅更高的临界电场的材料层。 阱区域和相邻边缘终止区域都设置在上层的上表面，并且氧化物层覆盖在上层和边缘终止区域上。 一种用于形成具有改进的边缘终止的硅模的方法。 该方法包括在重掺杂的硅衬底上形成包括第一导电类型的掺杂硅的上层，并形成边缘终止区，该边缘终止区包括在上层的上表面处具有比硅更高的临界电场的材料层 层。 第二相反导电类型的阱区形成在邻近边缘终止区的上层的上表面处，并且在上层和边缘终止区上形成氧化物层。

公开(公告)号：US06373098B1

公开(公告)日：2002-04-16

申请号：US09318334

申请日：1999-05-25

申请人： Linda S. Brush ,  Jun Zeng ,  Christopher B. Kocon

发明人： Linda S. Brush ,  Jun Zeng ,  Christopher B. Kocon

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/41766 ,  H01L29/42308 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7813

摘要： An improved trench-gated power device comprises a substrate having an overlying layer of epitaxial material disposed on an upper layer of the substrate, well regions containing source and body regions, a trench gate, and a drain region. The improvement comprises a gate trench having beneficially smooth sidewalls that comprise selectively grown epitaxial material and body regions that are recessed with respect to adjacent source regions. In a process for forming an improved trench-gated power device, a dielectric layer having an upper surface and thickness and width dimensions that substantially correspond to the height and width dimensions of a gate trench is formed on an upper layer of the substrate. A layer of epitaxial material is grown on the upper layer of the substrate and the dielectric layer and planarized to be substantially coplanar with the upper surface of the dielectric layer, which is then removed, thereby forming gate trench sidewalls that comprise selectively grown epitaxial material. The process further comprises lining the trench with a dielectric material and substantially filling the lined trench with a conductive material, thereby forming a trench gate, and forming well, body, and source regions in the planarized epitaxial material.

摘要翻译： 改进的沟槽门控功率器件包括具有设置在衬底的上层上的外延材料的重叠层的衬底，包含源极和体区的阱区，沟槽栅极和漏极区。 该改进包括具有有利的平滑侧壁的栅极沟槽，其包括选择性地生长的外延材料和相对于相邻源极区域凹陷的主体区域。 在用于形成改进的沟槽门控功率器件的工艺中，在衬底的上层上形成具有上表面的电介质层和基本对应于栅极沟槽的高度和宽度尺寸的厚度和宽度尺寸。 在衬底的上层和电介质层上生长一层外延材料，并将其平坦化为与电介质层的上表面基本上共面，然后将其除去，从而形成包含选择性生长的外延材料的栅沟槽侧壁。 该工艺还包括用介电材料衬套沟槽，并用导电材料基本上填充衬里的沟槽，从而形成沟槽栅极，并在平坦化的外延材料中形成阱，体和源极区。

公开(公告)号：US06188105B1

公开(公告)日：2001-02-13

申请号：US09283531

申请日：1999-04-01

申请人： Christopher B. Kocon ,  Jun Zeng

发明人： Christopher B. Kocon ,  Jun Zeng

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7455

摘要： A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.

摘要翻译： 高密度MOS门控器件包括半导体衬底和设置在衬底上的第一导电类型的掺杂上层。 上层包括第一导电类型的重掺杂源区和在上表面处的第二和相反导电类型的掺杂阱区。 包括源极区域的接触区域的上表面还包括凹陷部分，该凹陷部分包括位于凹陷部分下方的上层中的第二导电类型的重掺杂深体区域的接触区域。 该器件还包括设置在上层中并包括通过绝缘层与上层隔离的导电材料的沟槽栅极。 一种用于形成高密度MOS门控器件的方法包括提供包括第一导电类型的掺杂上层的半导体衬底。 第二和相反导电类型的掺杂阱区形成在上层的上表面，并且第一导电类型的掺杂剂注入阱区以形成重掺杂的源极区。 在上层的上表面上形成氮化物层，并且选择性地蚀刻氮化物层和上层，从而在上层形成沟槽。 沟槽衬有绝缘层，然后填充导电材料以形成沟槽栅极。 去除氮化物层，并且在沟槽栅极和上层的上表面上形成层间介电材料层。 选择性地蚀刻层间电介质层，从而形成源极区接触面积。 选择性地蚀刻源极区域以形成提供体区域接触面积的浅凹部。 将第二导电类型的掺杂剂注入到凹部中，从而形成凹陷下方的深体区域。

公开(公告)号：US6121089A

公开(公告)日：2000-09-19

申请号：US92334

申请日：1998-06-05

申请人： Jun Zeng ,  Carl Franklin Wheatley, Jr.

发明人： Jun Zeng ,  Carl Franklin Wheatley, Jr.

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66719 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/0626 ,  H01L29/0878

摘要： Methods of forming power semiconductor devices having merged split-well body regions include the steps of forming a semiconductor substrate containing a drift region of first conductivity type (e.g., N-type) therein extending to a first face thereof. First and second split-well body regions of second conductivity type (e.g., P-type) may also be formed at spaced locations in the drift region. First and second source regions of first conductivity type are also formed in the first and second split-well body regions, respectively. A central body/contact region of second conductivity type is also formed in the drift region, at a location intermediate the first and second split-well body regions. The central body/contact region preferably forms non-rectifying junctions with the first and second split-well body regions and a P-N rectifying junction with the drift region at a central junction depth which is less than the maximum well junction depths of the split-well body regions. First and second insulated gate electrodes may also be formed on the first face, opposite respective portions of the first and second split-well regions. Proper choice of drift region resistivity and implant conditions can be used to form a preferred dumbbell-shaped body region and move the location of breakdown within the device to a location which facilitates decoupling of device characteristics. A drift region extension of relatively high conductivity can also be provided along the bottom of the central body region to further limit the degree of coupling between device characteristics.

摘要翻译： 形成具有合并的分裂井体区域的功率半导体器件的方法包括以下步骤：在其第一面上形成包含第一导电类型（例如N型）的漂移区的半导体衬底。 第二导电类型的第一和第二分裂井体区域（例如P型）也可以形成在漂移区域中的间隔位置处。 第一导电类型的第一和第二源极区域也分别形成在第一和第二分裂阱体区域中。 第二导电类型的中心体/接触区域也形成在漂移区域中，在第一和第二分裂井体区域的中间位置处。 中心体/接触区域优选地形成与第一和第二分裂井体区域的非整流结，以及在中心结深度处的漂移区域的PN整流结，其小于分裂阱的最大阱结深度 身体区域。 第一和第二绝缘栅极电极也可以形成在第一面上，与第一和第二分裂阱区域的相应部分相对。 漂移区电阻率和植入条件的适当选择可以用于形成优选的哑铃形身体区域，并且将器件内的击穿位置移动到有助于器件特性解耦的位置。 还可以沿着中心体区域的底部提供相对高的导电性的漂移区域延伸，以进一步限制器件特性之间的耦合程度。

公开(公告)号：US09227189B2

公开(公告)日：2016-01-05

申请号：US12064630

申请日：2006-08-23

申请人： Daniel Sobek ,  Jun Zeng

发明人： Daniel Sobek ,  Jun Zeng

IPC分类号： G01N27/00 ,  B01L3/00 ,  F04B19/00 ,  G01N33/49

CPC分类号： B01L3/502792 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0645 ,  B01L2300/069 ,  B01L2300/089 ,  B01L2400/0415 ,  B01L2400/0448 ,  B01L2400/06 ,  F04B19/006 ,  G01N33/4905

摘要： A microfluidic liquid stream configuration system is provided including providing a substrate; forming a first co-planar electrode and a second co-planar electrode on the substrate; applying a dielectric layer, with a controlled surface energy, on the first co-planar electrode and the second co-planar electrode; forming an input reservoir on the first co-planar electrode and a second co-planar electrode; supplying a liquid in the input reservoir for analysis; and imposing an electric field, an electric field gradient, or a combination thereof on the liquid for respectively driving surface charge or dipole moments in the liquid for configuring a liquid stream.

摘要翻译： 提供了一种微流体液流配置系统，包括提供基板; 在所述基板上形成第一共面电极和第二共面电极; 在所述第一共平面电极和所述第二共面电极上施加具有受控表面能的电介质层; 在所述第一共平面电极和第二共面电极上形成输入容器; 在输入容器中供应液体进行分析; 并在液体上施加电场，电场梯度或其组合，以分别驱动用于构成液体流的液体中的表面电荷或偶极矩。