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    Semiconductor device fabricated by selective epitaxial growth method
    33.
    发明授权
    Semiconductor device fabricated by selective epitaxial growth method 有权
    通过选择性外延生长法制造的半导体器件

    公开(公告)号：US07679147B2

    公开(公告)日：2010-03-16

    申请号：US12230373

    申请日：2008-08-28

    申请人： Masahiro Fukuda ,  Yosuke Shimamune ,  Masaaki Koizuka ,  Katsuaki Ookoshi

    发明人： Masahiro Fukuda ,  Yosuke Shimamune ,  Masaaki Koizuka ,  Katsuaki Ookoshi

    IPC分类号： H01L47/00

    CPC分类号： H01L29/7833 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

    摘要翻译： 提高外延生长中的选择性的半导体器件。 提供了一种半导体器件，其包括形成在作为半导体衬底的Si衬底上的栅电极，其间具有栅极绝缘膜，并且在栅电极的侧面上形成含有卤素元素的绝缘层。 利用该半导体器件，当在Si衬底上形成SiGe层时，在栅电极的侧面上形成含有卤素元素的氮化硅膜。 因此，SiGe层以高选择性外延生长在Si衬底上。 结果，抑制了在例如栅电极和源极/漏极区域之间流动的截止状态的漏电流，并且建立了适合于实际批量生产的制造工艺。

    Semiconductor device fabricated by selective epitaxial growth method
    35.
    发明授权
    Semiconductor device fabricated by selective epitaxial growth method 有权
    通过选择性外延生长法制造的半导体器件

    公开(公告)号：US07446394B2

    公开(公告)日：2008-11-04

    申请号：US11717205

    申请日：2007-03-13

    申请人： Masahiro Fukuda ,  Yosuke Shimamune ,  Masaaki Koizuka ,  Katsuaki Ookoshi

    发明人： Masahiro Fukuda ,  Yosuke Shimamune ,  Masaaki Koizuka ,  Katsuaki Ookoshi

    IPC分类号： H01L23/58 ,  H01L21/20 ,  H01L21/471

    CPC分类号： H01L29/7833 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

    摘要翻译： 提高外延生长中的选择性的半导体器件。 提供了一种半导体器件，其包括形成在作为半导体衬底的Si衬底上的栅电极，其间具有栅极绝缘膜，并且在栅电极的侧面上形成并包含卤素元素的绝缘层。 利用该半导体器件，当在Si衬底上形成SiGe层时，在栅电极的侧面上形成含有卤素元素的氮化硅膜。 因此，SiGe层以高选择性外延生长在Si衬底上。 结果，抑制了在例如栅电极和源极/漏极区域之间流动的截止状态的漏电流，并且建立了适合于实际批量生产的制造工艺。

    Semiconductor device and semiconductor device manufacturing method
    36.
    发明申请
    Semiconductor device and semiconductor device manufacturing method 审中-公开
    半导体器件和半导体器件制造方法

    公开(公告)号：US20070126036A1

    公开(公告)日：2007-06-07

    申请号：US11393656

    申请日：2006-03-31

    申请人： Hiroyuki Ohta ,  Akiyoshi Hatada ,  Yosuke Shimamune ,  Akira Katakami ,  Naoyoshi Tamura

    发明人： Hiroyuki Ohta ,  Akiyoshi Hatada ,  Yosuke Shimamune ,  Akira Katakami ,  Naoyoshi Tamura

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7834 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device is configured so that there is formed a stressor film 4 covering the first field effect transistor and the second field effect transistor, formed with openings from which the originating area and the terminating area of each of the first field effect transistor and the second field effect transistor are partially exposed, and applying a stress to at least an area extending from the vicinity of the originating area to the vicinity of the terminating area of each of the first field effect transistor and the second field effect transistor, and that a height of a first gate electrode 3 (3A) in a direction substantially perpendicular to a first insulating layer is set different from a height of a second electrode 3 (3B) in the direction substantially perpendicular to a second insulating layer.

    摘要翻译： 半导体器件被配置为使得形成有覆盖第一场效应晶体管和第二场效应晶体管的应力器膜4，第一场效应晶体管和第二场效应晶体管形成有开口，第一场效应晶体管和第二场效应晶体管的起始区域和终止区域从该开口 场效应晶体管部分露出，并且对至少从始发区域附近延伸到第一场效应晶体管和第二场效应晶体管的端接区域附近的区域施加应力， 在基本上垂直于第一绝缘层的方向上的第一栅电极3（3A）的设置与第二电极3（3B）的高度基本上垂直于第二绝缘层的方向设定。

    Semiconductor device fabrication method
    38.
    发明申请
    Semiconductor device fabrication method 有权
    半导体器件制造方法

    公开(公告)号：US20060281288A1

    公开(公告)日：2006-12-14

    申请号：US11220865

    申请日：2005-09-08

    申请人： Kazuo Kawamura ,  Yosuke Shimamune

    发明人： Kazuo Kawamura ,  Yosuke Shimamune

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28525 ,  H01L21/76829 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： The semiconductor device fabrication method comprising the step of forming a gate electrode 54p on a semiconductor substrate 34; the step of forming a source/drain diffused layer 64p in the semiconductor substrate 34 on both sides of the gate electrode 54p; the step of burying a silicon germanium layer 100b in the source/drain diffused layer 64p; the step of forming an amorphous layer at an upper part of the silicon germanium layer 101; the step of forming a nickel film 66 on the amorphous layer 101; and the step of making thermal processing to react the nickel film 66 and the amorphous layer 101 with each other to form a silicide film 102b on the silicon germanium layer 100b. Because of no crystal boundaries in the amorphous layer 101 to react with the nickel film 66, the silicidation homogeneously goes on. Because of no crystal faces in the amorphous layer 101, the Ni(Si1-xGex)2 crystals are prevented from being formed in spikes. Thus, even when the silicon germanium layer 100b is silicided by using a thin nickel film 66, the sheet resistance can be low, and the junction leak current can be suppressed.

    摘要翻译： 半导体器件制造方法包括在半导体衬底34上形成栅电极54 p的步骤; 在栅极电极54 p的两侧在半导体衬底34中形成源极/漏极扩散层64 p的步骤; 在源极/漏极扩散层64 p中埋入硅锗层100b的步骤; 在硅锗层101的上部形成非晶层的步骤; 在非晶层101上形成镍膜66的步骤; 以及使热处理使镍膜66和非晶层101彼此反应以在硅锗层100b上形成硅化物膜102b的步骤。 由于非晶层101中没有晶体边界与镍膜66反应，因此硅化物均匀地继续进行。 由于在非晶层101中没有晶面，因此可以防止Ni（Si 1-x N 2）x O 2晶体形成于 尖峰。 因此，即使当通过使用薄的镍膜66硅化硅锗层100b时，薄层电阻也可以低，并且可以抑制结漏电流。

    Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor
    40.
    发明授权
    Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor 有权
    半导体器件的制造方法和动态阈值晶体管的制造方法

    公开(公告)号：US08709898B2

    公开(公告)日：2014-04-29

    申请号：US13552274

    申请日：2012-07-18

    申请人： Masahiro Fukuda ,  Eiji Yoshida ,  Yosuke Shimamune

    发明人： Masahiro Fukuda ,  Eiji Yoshida ,  Yosuke Shimamune

    IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/783 ,  H01L29/7848

    摘要： A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

    摘要翻译： 一种方法包括：除硅衬底部分之外，蚀刻硅衬底，在其上形成沟道区以在硅衬底部分的第一侧和第二侧分别形成第一和第二沟槽; 通过外延生长具有对硅蚀刻选择性的半导体层和另外的硅层来填充第一和第二沟槽; 通过选择性蚀刻工艺去除半导体层选择性，以在衬底部分的第一侧和第二侧分别在硅层下形成空隙; 至少部分地用掩埋绝缘膜掩埋空隙; 在所述硅衬底部分上形成栅极绝缘膜和栅电极; 以及在所述硅衬底部分的第一侧的所述硅层中形成源极区域以及在所述硅衬底部分的第二侧处形成漏极区域。