公开(公告)号：US07615813B2

公开(公告)日：2009-11-10

申请号：US11859388

申请日：2007-09-21

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L21/8234

CPC分类号： H01L23/5252 ,  H01L21/76229 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

摘要翻译： 在硅衬底内同时形成用于元件隔离的第一凹部，用于对准标记的第二凹部和用于反熔丝部的第三凹部。 在整个表面上形成氧化硅膜之后，去除位于第二和第三凹部内的氧化硅膜。 然后，在整个表面上形成栅极绝缘膜，然后在栅极绝缘膜上形成多晶硅膜。 此外，选择性地去除这些多晶硅膜和栅极绝缘膜，以在元件区域上方形成栅电极，在第二凹部中形成对准标记部分，在第三凹部的底表面上形成用于反熔丝部分的栅电极 一部分。

公开(公告)号：US07605042B2

公开(公告)日：2009-10-20

申请号：US11107843

申请日：2005-04-18

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L21/336

CPC分类号： H01L29/8126 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/42316 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

摘要翻译： 描述了用于制造这种结构的半导体器件结构和方法，其提供完全掺杂的晶体管源极/漏极区域，同时减少或甚至避免硼渗入晶体管沟道，从而改善晶体管的性能。 此外，这种晶体管可以从对晶体管沟道施加压缩应力的SiGe层受益，从而进一步改善晶体管的性能。

公开(公告)号：US20080012057A1

公开(公告)日：2008-01-17

申请号：US11859388

申请日：2007-09-21

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L29/94

CPC分类号： H01L23/5252 ,  H01L21/76229 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first concave portion for the element isolation, a second concave portion for an aligning mark, and a third concave portion for an anti-fuse portion are formed simultaneously within a silicon substrate. After a silicon oxide film is formed on the entire surface, the silicon oxide film positioned within the second and third concave portions is removed. Then, a gate insulating film is formed on the entire surface, followed by forming a polysilicon film on the gate insulating film. Further, these polysilicon film and gate insulating film are selectively removed to form a gate electrode above an element region, an aligning mark portion in the second concave portion, and a gate electrode for an anti-fuse portion on the bottom surface of the third concave portion.

摘要翻译： 在硅衬底内同时形成用于元件隔离的第一凹部，用于对准标记的第二凹部和用于反熔丝部的第三凹部。 在整个表面上形成氧化硅膜之后，去除位于第二和第三凹部内的氧化硅膜。 然后，在整个表面上形成栅极绝缘膜，然后在栅极绝缘膜上形成多晶硅膜。 此外，选择性地去除这些多晶硅膜和栅极绝缘膜，以在元件区域上方形成栅电极，在第二凹部中形成对准标记部分，在第三凹部的底表面上形成用于反熔丝部分的栅电极 一部分。

公开(公告)号：US07187027B2

公开(公告)日：2007-03-06

申请号：US11333412

申请日：2006-01-18

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

摘要翻译： 第一和第二布线形成在第一绝缘膜上。 每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。 此后，在整个表面上形成氧化硅绝缘膜。 蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。 由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。 此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。

公开(公告)号：US20070045747A1

公开(公告)日：2007-03-01

申请号：US11211604

申请日：2005-08-26

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L29/76

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823871

摘要： Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

摘要翻译： 描述了减少在拉伸和压缩衬里（T-C边界）之间的边界处的不同电位的触点之间发生意外的地铁短路的可能性。 这可以在不过度增加半导体器件的尺寸的情况下进行，或者甚至在以前的设计中增加尺寸。 例如，简单地通过调整装置的布局，两个不同公共栅极的触点可以相对于T-C边界相反的方向偏移。 或者，通过形成具有锯齿形或其他类似图案的T-C边界，可以将触点设置得更靠近在一起，同时仍然减少了地铁短路形成的可能性。 这样的布局调整不需要额外的步骤或成本。

公开(公告)号：US20060234432A1

公开(公告)日：2006-10-19

申请号：US11107843

申请日：2005-04-18

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L21/338 ,  H01L21/20

CPC分类号： H01L29/8126 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/42316 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor

摘要翻译： 描述了用于制造这种结构的半导体器件结构和方法，其提供完全掺杂的晶体管源极/漏极区域，同时减少或甚至避免硼渗入晶体管沟道，从而改善晶体管的性能。 此外，这种晶体管可以从对晶体管沟道施加压缩应力的SiGe层受益，从而进一步提高晶体管的性能

公开(公告)号：US20060231826A1

公开(公告)日：2006-10-19

申请号：US11107838

申请日：2005-04-18

申请人： Yusuke Kohyama

发明人： Yusuke Kohyama

IPC分类号： H01L31/00

CPC分类号： H01L29/665 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.

摘要翻译： 一种器件及其制造方法，包括具有嵌入SiGe层的PFET，其中SiGe层的浅部更靠近PFET沟道，并且SiGe层的深部分远离PFET沟道。 因此，SiGe层在面向通道的一侧上具有渐缩的边界。 这种配置可以允许PFET通道被大量的压缩应力，而不必基本上降低延伸结特性。 锥形SiGe边界可以被配置为多个离散步骤。 例如，可以形成两个，三个或更多个离散步骤。

公开(公告)号：US06593202B2

公开(公告)日：2003-07-15

申请号：US09909790

申请日：2001-07-23

申请人： Keiji Hosotani ,  Yusuke Kohyama

发明人： Keiji Hosotani ,  Yusuke Kohyama

IPC分类号： H01L2120

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

摘要翻译： 在制造COB DRAM单元的方法中，在与栅电极自对准的源极和漏极上形成多晶硅插塞。 在多晶硅插塞上形成位线接触和存储电极接触，从而减小位线接触和存储电极接触的纵横比。 由于多晶硅插塞形成与栅极电极自对准，不会发生相邻元件区域的触点短路和源极和漏极的插头短路，从而导致高度的不对准保护。 此外，不需要独立的光刻工艺来形成多晶硅插塞，因此，制造步骤的数量减少。

公开(公告)号：US06551894B1

公开(公告)日：2003-04-22

申请号：US09631830

申请日：2000-08-03

申请人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

发明人： Yusuke Kohyama ,  Takashi Ohsawa ,  Shizuo Sawada

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

摘要翻译： 第一和第二布线形成在第一绝缘膜上。 每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。 此后，在整个表面上形成氧化硅绝缘膜。 蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。 由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。 此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。

公开(公告)号：US06403444B2

公开(公告)日：2002-06-11

申请号：US09800915

申请日：2001-03-08

申请人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

发明人： Yoshiaki Fukuzumi ,  Yusuke Kohyama

IPC分类号： H01L2120

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/86 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91

摘要： This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

摘要翻译： 本发明提供一种电容器及其制造方法，该电容器包括具有波状形状和改善的电极面积的金属下电极。 用于数据存储的电容器经由具有接触插塞的绝缘夹层形成在半导体衬底（未示出）上。 电容器具有内表面和外表面粗糙或起伏的下电极，使得一个表面具有符合另一表面形状的形状，形成为覆盖下电极的表面的电介质膜和形成为 通过电介质膜覆盖下电极。 下电极具有开口上端的圆柱形。 下电极通过接触插头连接到单元晶体管。 下电极由金属或金属氧化物形成。