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    STRUCTURES AND METHODS FOR ELECTRICALLY AND MECHANICALLY LINKED MONOLITHICALLY INTEGRATED TRANSISTOR AND MEMS/NEMS DEVICES
    3.
    发明申请
    STRUCTURES AND METHODS FOR ELECTRICALLY AND MECHANICALLY LINKED MONOLITHICALLY INTEGRATED TRANSISTOR AND MEMS/NEMS DEVICES 有权
    电力和机械连接的单相集成晶体管和MEMS / NEMS器件的结构和方法

    公开(公告)号：US20130328109A1

    公开(公告)日：2013-12-12

    申请号：US13990830

    申请日：2011-12-01

    申请人： Amit Lal ,  Kwame Amponsah

    发明人： Amit Lal ,  Kwame Amponsah

    IPC分类号： H01L25/16 ,  H01L29/66

    CPC分类号： H01L25/16 ,  B81C1/00246 ,  B81C2203/075 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/735 ,  H01L29/8086 ,  H01L29/8126 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated; its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.) In one embodiment, devices according to the present invention were realized in 2?m thick SOI cross-wire beams, with a MoSi2 contact metallization for stress minimization and ohmic contact. In this embodiment, the pull-in voltage for the MEMS cantilever was 21V and the pinch-off voltage of the JFET was −19V.

    摘要翻译： 包括NEMS / MEMS机器和相关联的电路的装置。 该电路包括至少一个晶体管，优选JFET，其用于：（i）致动NEMS / MEMS机器; 和/或（ii）从NEMS / MEMS机器的操作接收反馈晶体管（例如，JFET）和NEMS / MEMS机器是单片集成的，用于增强的信号传导和信号处理。 由于减少寄生和失配，整体集成优于混合集成（例如，使用引线键合，倒装芯片接触键等的集成）。 在一个实施例中，JFET直接集成在MEMS机器中，其是以SOI MEMS悬臂的形式，以形成感测和电子集成之间的非常紧密的集成。 当连接到JFET的悬臂被静电驱动时; 其运动通过单片集成导电路径（例如，迹线，通孔等）直接影响JFET中的电流。在一个实施例中，根据本发明的器件在2μm厚的SOI交叉线束中实现，其中MoSi 2 接触金属化用于应力最小化和欧姆接触。 在本实施例中，MEMS悬臂的拉入电压为21V，JFET的截止电压为-19V。

    INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL
    4.
    发明申请
    INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL 有权
    绝缘栅栏场效应晶体管有通道的肖特基屏障

    公开(公告)号：US20130140629A1

    公开(公告)日：2013-06-06

    申请号：US13757597

    申请日：2013-02-01

    申请人： Acorn Technologies, Inc.

    发明人： Daniel E. Grupp ,  Daniel J. Connelly

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

    摘要： A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

    摘要翻译： 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。 通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。 钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下面的底切空隙区域 。 金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。

    Thin film transistor having Schottky barrier
    5.
    发明授权
    Thin film transistor having Schottky barrier 有权
    具有肖特基势垒的薄膜晶体管

    公开(公告)号：US08410531B2

    公开(公告)日：2013-04-02

    申请号：US13029101

    申请日：2011-02-16

    申请人： Ming-Tse Chang ,  Chun-Wei Su

    发明人： Ming-Tse Chang ,  Chun-Wei Su

    IPC分类号： H01L29/812

    CPC分类号： H01L51/0554 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/8126 ,  H01L29/872

    摘要： A thin film transistor having Schottky barrier includes a substrate, a first gate conductive layer formed on the substrate, a first semiconductor layer having a first conductive type formed on the first gate conductive layer, a source conductive layer and a drain conductive layer electrically isolated from each other and positioned on the first semiconductor layer, a second semiconductor layer having a second conductive type formed on the source conductive layer and the drain conductive layer, and a second gate conductive layer formed on the second semiconductor layer. The first conductive type is complementary to the second conductive type.

    摘要翻译： 具有肖特基势垒的薄膜晶体管包括衬底，形成在衬底上的第一栅极导电层，形成在第一栅极导电层上的第一导电类型的第一半导体层，与第一栅极导电层电隔离的源极导电层和漏极导电层 彼此并且位于第一半导体层上，在源极导电层和漏极导电层上形成具有第二导电类型的第二半导体层，以及形成在第二半导体层上的第二栅极导电层。 第一导电类型与第二导电类型互补。

    Insulated gate field effect transistor having passivated schottky barriers to the channel
    7.
    发明授权
    Insulated gate field effect transistor having passivated schottky barriers to the channel 有权
    绝缘栅场效应晶体管具有通道的钝化肖特基势垒

    公开(公告)号：US07883980B2

    公开(公告)日：2011-02-08

    申请号：US11403185

    申请日：2006-04-11

    申请人： Daniel E. Grupp ,  Daniel J. Connelly

    发明人： Daniel E. Grupp ,  Daniel J. Connelly

    IPC分类号： H01L21/336

    CPC分类号： H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

    摘要： A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

    摘要翻译： 晶体管包括设置在栅极附近并且在源极和漏极之间的电气路径中的半导体沟道，其中所述沟道和源极或漏极中的至少一个由界面层分开以形成沟道界面层 源极/漏极结，其中半导体通道的费米能级在接合点附近的区域中被取代，并且该结具有小于约1000Ω的比接触电阻。 界面层可以包括通道的半导体的钝化材料，例如氮化物，氟化物，氧化物，氧氮化物，氢化物和/或砷化物。 在一些情况下，界面层基本上由被配置为消除通道的半导体的费米能级的单层或者足以终止半导体通道的全部或足够数量的悬挂键以达到化学稳定性的钝化材料的量 的表面。 此外，界面层可以包括与钝化材料不同的材料的分离层。 在使用时，分离层具有足以减少半导体通道中金属诱发的间隙状态的影响的厚度。

    Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances
    10.
    发明授权
    Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances 失效
    具有降低的寄生电容的场效应晶体管类型的III族氮化物半导体器件

    公开(公告)号：US06765241B2

    公开(公告)日：2004-07-20

    申请号：US10362883

    申请日：2003-02-27

    申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

    发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

    IPC分类号： H01L29812

    CPC分类号： H01L29/8126 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003

    摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.

    摘要翻译： 具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。 该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。 在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。 所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。