公开(公告)号：US07279949B2

公开(公告)日：2007-10-09

申请号：US11215416

申请日：2005-08-30

申请人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

发明人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Daniel J. Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael A. Sperling

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00039

摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

摘要翻译： 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

公开(公告)号：US20060181324A1

公开(公告)日：2006-08-17

申请号：US11215416

申请日：2005-08-30

申请人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

发明人： Daniel Dreps ,  Frank Ferraiolo ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Michael Sperling

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00039

摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

摘要翻译： 公开了具有无毛刺操作的延迟元件和延迟线。 作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器 用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数 由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

公开(公告)号：US20060164059A1

公开(公告)日：2006-07-27

申请号：US11040225

申请日：2005-01-21

申请人： Daniel Dreps ,  Seongwon Kim ,  Michael Sperling

发明人： Daniel Dreps ,  Seongwon Kim ,  Michael Sperling

IPC分类号： G05F3/04 ,  G05F3/08

CPC分类号： H03K5/08 ,  G01R19/16552 ,  G01R29/26

摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.

摘要翻译： 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。 这具有以不需要校准的方式直接感测电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

公开(公告)号：US09269042B2

公开(公告)日：2016-02-23

申请号：US12895791

申请日：2010-09-30

申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

公开(公告)号：US07932705B2

公开(公告)日：2011-04-26

申请号：US12178678

申请日：2008-07-24

申请人： Seongwon Kim ,  Daniel M. Dreps

发明人： Seongwon Kim ,  Daniel M. Dreps

IPC分类号： G05F1/563 ,  G05F1/59 ,  G05F5/08

CPC分类号： G05F1/561

摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.

摘要翻译： 可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。 可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。

公开(公告)号：US07859318B2

公开(公告)日：2010-12-28

申请号：US12030946

申请日：2008-02-14

申请人： Daniel Dreps ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Glen Wiedemeier

发明人： Daniel Dreps ,  Daniel Friedman ,  Seongwon Kim ,  Hector Saenz ,  Glen Wiedemeier

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator.

摘要翻译： 稳定的延迟线装置包括耦合到节点的主调节器和耦合到节点的多个延迟分支，以通过主调节器接收到节点的电压输出。 多个延迟分支中的每一个包括微调节器和延迟线。 延迟线耦合到微调节器，使得在每个延迟分支处通过相应的微调节器局部去除未滤波的噪声。

公开(公告)号：US20100019744A1

公开(公告)日：2010-01-28

申请号：US12178678

申请日：2008-07-24

申请人： Seongwon Kim ,  Daniel M. Dreps

发明人： Seongwon Kim ,  Daniel M. Dreps

IPC分类号： G05F1/10

CPC分类号： G05F1/561

摘要： A variable input voltage regulator includes a first circuit configured to convert a first voltage from a first voltage source to a first current, and a second circuit electrically coupled to the first circuit and configured to mirror the first current to a voltage output node. The variable input voltage regulator further includes a third circuit electrically coupled to the voltage output node of the second circuit and configured to supply additional current to the voltage output node from a second voltage of a second voltage source in response to a control input.

摘要翻译： 可变输入电压调节器包括被配置为将第一电压从第一电压源转换为第一电流的第一电路，以及电耦合到第一电路并被配置为将第一电流镜像到电压输出节点的第二电路。 可变输入电压调节器还包括电耦合到第二电路的电压输出节点并被配置为响应于控制输入从第二电压源的第二电压向电压输出节点提供附加电流的第三电路。

公开(公告)号：US20090059627A1

公开(公告)日：2009-03-05

申请号：US11847416

申请日：2007-08-30

申请人： Seongwon Kim

发明人： Seongwon Kim

IPC分类号： H02M1/12 ,  G05F1/10

CPC分类号： G05F1/467

摘要： A linear voltage regulator is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range.

摘要翻译： 提供线性稳压器。 线性稳压器包括被配置为从电压源接收第一电压并且去除第一频率范围中的第一电压的频率分量以获得主输出节点处的输出电压的第一电路。 线性电压调节器还包括具有电耦合到第一电路的主输出节点的第一和第二反相器的第二电路。 第二电路被配置为接收输出电压并且在第二频率范围中去除输出电压的频率分量。 第二个频率范围大于第一个频率范围。

公开(公告)号：US07412640B2

公开(公告)日：2008-08-12

申请号：US10650222

申请日：2003-08-28

申请人： Mohit Kapur ,  Seongwon Kim

发明人： Mohit Kapur ,  Seongwon Kim

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： H04L1/242

摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

摘要翻译： 提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。 被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。 在本发明的一个方面，PRBS检查技术包括以下步骤/操作。 对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。 错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。 然后，错误位的传播在后续的时钟周期被禁止。 禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

公开(公告)号：US07301320B2

公开(公告)日：2007-11-27

申请号：US11040225

申请日：2005-01-21

申请人： Daniel M. Dreps ,  Seongwon Kim ,  Michael A. Sperling

发明人： Daniel M. Dreps ,  Seongwon Kim ,  Michael A. Sperling

IPC分类号： G05F5/00 ,  H02J1/02

CPC分类号： H03K5/08 ,  G01R19/16552 ,  G01R29/26

摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.

摘要翻译： 片上电源噪声传感器检测电源电压的高频超频和欠压。 通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。 通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。 这具有以不需要校准的方式直接感测电源噪声的优点。 此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。 最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。