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97 条记录 (耗时 0.046 秒)

    Pixel information readout method and image pickup apparatus
    31.
    发明授权
    Pixel information readout method and image pickup apparatus 有权
    像素信息读出方法和图像拾取装置

    公开(公告)号：US07944482B2

    公开(公告)日：2011-05-17

    申请号：US11826865

    申请日：2007-07-19

    申请人： Kuniyuki Tani ,  Tohru Watanabe

    发明人： Kuniyuki Tani ,  Tohru Watanabe

    IPC分类号： H04N5/228 ,  H04N5/235

    CPC分类号： H04N5/2351 ,  H04N5/23254 ,  H04N5/23274 ,  H04N5/2329 ,  H04N5/341 ,  H04N5/3456 ,  H04N5/3458 ,  H04N5/3535

    摘要： When successively reading out pixel information from an image region, where image pickup devices are arranged two-dimensionally, which is divided into a plurality of sub-regions, a readout unit inserts pixel information on pixels of interest in the respective sub-regions successively at predetermined intervals and reads them out. A control unit generates a frame from the pixel information, on pixels of interest inserted at the predetermined intervals, which has been read out from the readout unit. The control unit grasps a tendency of a picked-up image from the generated frame and performs a predetermined adaptive control according to the grasped tendency.

    摘要翻译： 当从分割成多个子区域的二维地排列图像拾取装置的图像区域连续地读出像素信息时，读出单元将各个子区域中的关注像素的像素信息连续地插入到各个子区域 预定间隔并读出。 控制单元从已经从读出单元读出的以预定间隔插入的感兴趣的像素上的像素信息生成帧。 控制单元从所生成的帧中抓取拍摄图像的趋势，并根据所掌握的趋势执行预定的自适应控制。

    Image capturing device
    33.
    发明授权
    Image capturing device 失效
    图像捕捉设备

    公开(公告)号：US07355640B2

    公开(公告)日：2008-04-08

    申请号：US10648772

    申请日：2003-08-25

    申请人： Tatsuya Takahashi ,  Tohru Watanabe ,  Osamu Tabata

    发明人： Tatsuya Takahashi ,  Tohru Watanabe ,  Osamu Tabata

    IPC分类号： H04N9/64

    CPC分类号： H04N5/361 ,  H04N5/3655 ,  H04N5/3722

    摘要： An image capturing device having a function of clamping an image signal. When the image capturing device is activated, a synchronous signal generating section begins creation of a horizontal synchronous signal, and a counter begins counting a pulse of the horizontal synchronous signal. When the counted value reaches a predetermined value, the clamping capability control section changes the level of a clamp mode signal to an H level. During a period from the start of power supply to the image capturing device to the raising of the level of a clamp mode signal to an H level, a clamp pulse generating section sets a longer width for a clamp pulse than in a normal operation so that a switch element of a clamping circuit remains in an on state in a longer period, whereby a smaller time constant for clamping is set. After elapse of a predetermined period, the switch element is controlled so as to remain in an ON state in a normal period, which is relatively short, whereby a larger time constant for clamping is set. With this arrangement, noise which would be caused with a small clamping time constant is suppressed.

    摘要翻译： 具有夹持图像信号的功能的图像捕获装置。 当图像拍摄装置被激活时，同步信号产生部分开始创建水平同步信号，并且计数器开始计数水平同步信号的脉冲。 当计数值达到预定值时，钳位能力控制部分将钳位模式信号的电平改变为H电平。 在从供电开始到图像捕获装置到将钳位模式信号的电平提高到H电平的期间中，钳位脉冲发生部分将钳位脉冲的宽度设置为比正常操作更长的宽度，使得 钳位电路的开关元件在较长时间内保持导通状态，由此设定较小的钳位时间常数。 在经过预定时间后，开关元件被控制成在相对较短的正常时段内保持在ON状态，由此设定较大的夹紧时间常数。 通过这种布置，可以抑制以小的夹紧时间常数引起的噪声。

    Deficient pixel detection method and image signal processor
    35.
    发明授权
    Deficient pixel detection method and image signal processor 失效
    缺陷像素检测方法和图像信号处理器

    公开(公告)号：US06768513B1

    公开(公告)日：2004-07-27

    申请号：US09680705

    申请日：2000-10-06

    申请人： Tohru Watanabe ,  Masato Teratani

    发明人： Tohru Watanabe ,  Masato Teratani

    IPC分类号： H04N964

    CPC分类号： H04N5/367

    摘要： An image signal processor detects deficient pixels, such as pixels having a white deficiency or a black deficiency, and corrects the image signal so that the pixel deficiency is not reproduced. A memory circuit holds a target pixel signal and peripheral signals, which correspond to the pixels adjacent to the target pixel. A deficiency detection circuit compares the level of the target pixel signal with the levels of the peripheral pixel signals to detect whether the target pixel is deficient. A deficiency correction circuit corrects the signal of a detected deficient pixel using information from nearby pixels.

    摘要翻译： 图像信号处理器检测诸如具有白色不足或黑色不足的像素的缺陷像素，并校正图像信号，使得不再现像素缺陷。 存储电路保持对象像素信号和对应于与目标像素相邻的像素的周边信号。 缺陷检测电路将目标像素信号的电平与周边像素信号的电平进行比较，以检测目标像素是否不足。 缺陷校正电路使用来自附近像素的信息校正检测到的缺陷像素的信号。

    Solid-state image pickup apparatus
    36.
    发明授权
    Solid-state image pickup apparatus 失效
    固态摄像装置

    公开(公告)号：US06545713B1

    公开(公告)日：2003-04-08

    申请号：US09014944

    申请日：1998-01-28

    申请人： Tohru Watanabe

    发明人： Tohru Watanabe

    IPC分类号： H04N314

    CPC分类号： H04N9/045 ,  H04N5/3452 ,  H04N5/347 ,  H04N5/3725

    摘要： In an output section (11d) of an image sensor (11), information charges are discharged from a capacitance at a reset clock &phgr;r1, which is twice the period of a horizontal clock &phgr;h, and the information charges for two pixels are accumulated in the capacitance. In two steps, a sample-and-hold circuit (14) inputs an image signal Y0(t) that is output from the output section (11d) and outputs an image signal Y1(t) in which a period representing the information charge for one pixel and a period representing the information charges for two pixels alternately repeat. By taking the difference between the value of the period representing the information charges of two pixels and the value of the period representing the information charge of one pixel in the image signal Y1(t), the information charge of each pixel can be individually determined.

    摘要翻译： 在图像传感器（11）的输出部分（11d）中，信息电荷从水平时钟phih周期的两倍的复位时钟phir1处的电容放电，并且两个像素的信息电荷被累积在 电容。 在两个步骤中，采样和保持电路（14）输入从输出部分（11d）输出的图像信号Y0（t），并输出图像信号Y1（t），其中表示用于 一个像素和一个表示两个像素的信息费用的周期交替重复。 通过取代表示图像信号Y1（t）中的两个像素的信息电荷的周期的值与表示一个像素的信息电荷的周期的值之间的差，可以单独确定每个像素的信息电荷。

    Signal processor system with noise suppression
    37.
    发明授权
    Signal processor system with noise suppression 失效
    具有噪声抑制功能的信号处理器系统

    公开(公告)号：US06377199B1

    公开(公告)日：2002-04-23

    申请号：US09320828

    申请日：1999-05-26

    申请人： Tohru Watanabe

    发明人： Tohru Watanabe

    IPC分类号： H03M112

    CPC分类号： H04N5/335 ,  G06J1/00 ,  H03M1/0845 ,  H03M1/12 ,  H04N5/217

    摘要： A mixed signal processor includes an analog processor, a digital signal processor, an A/D converter connected between the two processors, a pair of output circuits, and a complementary data generating circuit connected between the output circuits and the digital signal processor. The complementary data generating circuit receives a digital data signal output from the processor and generates a delayed data signal and a complementary signal. The complementary or sub-data signal is generated by inverting the data signal when there is no change between corresponding consecutive bits of the digital signal and maintaining or not inverting the data signal when corresponding consecutive bits of the digital signal are different. The complementary data generating circuit causes a sum of the currents flowing to the respective output circuits to remain constant even when the data bits are changing, which suppresses noise generation which could adversely effect the operation of the analog signal processor.

    摘要翻译： 混合信号处理器包括模拟处理器，数字信号处理器，连接在两个处理器之间的A / D转换器，一对输出电路和连接在输出电路和数字信号处理器之间的互补数据产生电路。 互补数据产生电路接收从处理器输出的数字数据信号，并生成延迟数据信号和互补信号。 互补或子数据信号是通过在数字信号的相应的连续位之间没有变化时反转数据信号，并且当数字信号的相应连续位不同时保持或不反相数据信号而产生。 互补数据产生电路，即使在数据位发生变化时，流向各输出电路的电流的和也保持恒定，这抑制可能不利地影响模拟信号处理器的操作的噪声产生。

    Image data compressing apparatus
    39.
    发明授权
    Image data compressing apparatus 失效
    图像数据压缩装置

    公开(公告)号：US5410352A

    公开(公告)日：1995-04-25

    申请号：US23214

    申请日：1993-02-25

    申请人： Tohru Watanabe

    发明人： Tohru Watanabe

    IPC分类号： H04N1/41 ,  G06T9/00 ,  H04N11/04 ,  H04N19/126 ,  H04N19/13 ,  H04N19/134 ,  H04N19/146 ,  H04N19/149 ,  H04N19/167 ,  H04N19/169 ,  H04N19/172 ,  H04N19/189 ,  H04N19/192 ,  H04N19/196 ,  H04N19/423 ,  H04N19/436 ,  H04N19/60 ,  H04N19/625 ,  H04N19/85 ,  H04N19/91 ,  H04N7/133

    CPC分类号： H04N19/423 ,  H04N19/126 ,  H04N19/15 ,  H04N19/176 ,  H04N19/184 ,  H04N19/192 ,  H04N19/60 ,  H04N19/146

    摘要： An image data compressing apparatus comprises a transform unit, such as a DCT computation unit, a quantization table memory for plural types of quantization tables, a quantizer which selectively uses the quantization tables, a coder for performing coding in accordance with a pre-given predicted value for the amount of generated codes of each block, memories for storing the amounts of codes for DC components and AC components generated for the individual blocks, a computation unit for computing the sum of the amounts of generated codes for DC components and the sum of the amounts of generated codes for AC components for each properly selected quantization table, and memories for storing the computed sums of the amounts of generated codes, wherein the apparatus uses a plurality of quantization tables to predict a change in the amount of generated codes caused by the alteration of the quantization table in the first compression, and compresses image data to the target amount of generated codes in the second compression.

    摘要翻译： 图像数据压缩装置包括诸如DCT计算单元的变换单元，用于多种类型的量化表的量化表存储器，选择性地使用量化表的量化器，用于根据预先给定的预测进行编码的编码器 每个块的生成代码量的值，用于存储针对各个块生成的DC分量的代码量的存储器和用于计算DC分量的生成代码量之和的计算单元， 用于每个适当选择的量化表的AC分量的生成代码量以及用于存储计算出的所生成代码量的和的存储器，其中该装置使用多个量化表来预测由...产生的代码量的变化量 第一压缩中的量化表的改变，并将图像数据压缩到所生成的目标量 代码在第二次压缩。

    Integrated circuit for processing digital signals in video camera having electronic zooming function
    40.
    发明授权
    Integrated circuit for processing digital signals in video camera having electronic zooming function 失效
    用于处理具有电子变焦功能的摄像机中的数字信号的集成电路

    公开(公告)号：US5331411A

    公开(公告)日：1994-07-19

    申请号：US784228

    申请日：1991-10-29

    申请人： Kiyotada Kawakami ,  Masao Takuma ,  Tooru Asaeda ,  Tooru Yamamoto ,  Haruhiko Murata ,  Hirotsugu Murashima ,  Tohru Watanabe ,  Masashi Honzawa ,  Keiichi Tanii

    发明人： Kiyotada Kawakami ,  Masao Takuma ,  Tooru Asaeda ,  Tooru Yamamoto ,  Haruhiko Murata ,  Hirotsugu Murashima ,  Tohru Watanabe ,  Masashi Honzawa ,  Keiichi Tanii

    IPC分类号： H04N5/225 ,  H04N5/262 ,  H04N9/07 ,  H04N9/64 ,  H04N9/74 ,  H04N3/223 ,  H04N5/232 ,  H04N9/04

    CPC分类号： H04N9/74 ,  H04N5/2628 ,  H04N2209/046

    摘要： An output from a solid state image sensing device spatially modulated by a color filter is A/D converted and stored in a field memory. Digital signals read from the field memory during electronic zooming are successively delayed by 1H period by means of first, second and third 1H delay elements connected in series. The output from the field memory and outputs from the first, second and third 1H delay elements are separated into luminance components and line sequential color components by first to fourth Y/C separating circuits, respectively. A first set of three primary color signals are calculated based on outputs from the first, second and third Y/C separating circuits, and a second set of three primary color signals are calculated based on outputs from the second, third and fourth Y/C separating circuits. Three primary color signals corresponding to a new display point formed along with the execution of the electronic zooming function are formed based on the calculated two sets of three primary color signals, and a luminance signal corresponding to the new display point is formed based on outputs from the second and third Y/C separating circuits.

    摘要翻译： 由滤色器空间调制的固态图像感测装置的输出被A / D转换并存储在场存储器中。 在电子变焦期间从现场存储器读取的数字信号通过串联连接的第一，第二和第三1H延迟元件连续延迟1H周期。 来自场存储器的输出和来自第一，第二和第三1H延迟元件的输出分别由第一至第四Y / C分离电路分离成亮度分量和行顺序颜色分量。 基于来自第一，第二和第三Y / C分离电路的输出计算第一组三原色信号，并且基于来自第二，第三和第四Y / C分离电路的输出来计算第二组三原色信号 分离电路。 基于计算出的两组三原色信号形成与执行电子缩放功能一起形成的新显示点的三原色信号，并且基于来自 第二和第三Y / C分离电路。