公开(公告)号：US5391912A

公开(公告)日：1995-02-21

申请号：US963696

申请日：1992-10-20

申请人： Masatada Horiuchi ,  Kazuo Nakazato

发明人： Masatada Horiuchi ,  Kazuo Nakazato

IPC分类号： H01L27/102 ,  H01L27/108 ,  H01L29/04 ,  H01L29/72

CPC分类号： H01L27/10841 ,  H01L27/1023

摘要： This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

摘要翻译： 本发明涉及一种半导体器件，其中主表面为（111）的主表面在与其垂直的方向上的主表面被蚀刻以形成垂直沟槽和横向沟槽的单晶半导体衬底形成在 通过相对于晶体轴进行各向异性蚀刻，使得蚀刻沿<110>轴方向前进，横向和垂直沟槽被多晶或非晶半导体或绝缘体填充，从而垂直沟槽的侧壁。

公开(公告)号：US4558680A

公开(公告)日：1985-12-17

申请号：US579066

申请日：1984-02-10

申请人： Kazuo Nakazato

发明人： Kazuo Nakazato

IPC分类号： F02D23/00 ,  F02M7/28 ,  F02M7/12

CPC分类号： F02D23/00 ,  F02M7/28 ,  Y02T10/144 ,  Y10S261/51

摘要： A system for controlling the air-fuel ratio for an engine comprises a first passage for communicating a portion adjacent to an inlet of an air bleed of a carburetor of the engine with a portion of the intake passage between an air-cleaner and a supercharger, a valve provided in the first passage, an actuator comprising a diaphragm operatively connected to the valve and first and second chambers defined by the diaphragm. A second passage is provided for communicating the first chamber with the intake passage at the upstream side of the inlet of the air bleed, and a third passage is provided for communicating the second chamber with the intake passage at the downstream side of a throttle valve of the engine. The actuator is so arranged that the valve opens when the difference between pressures in the first and second chambers exceeds a predetermined value, thereby supplying rich air-fuel mixture.

摘要翻译： 用于控制发动机的空燃比的系统包括第一通道，用于将与发动机的化油器的排气入口相邻的部分与进气通道的一部分在空气净化器和增压器之间连通， 设置在第一通道中的阀，致动器，其包括可操作地连接到阀的隔膜和由隔膜限定的第一和第二室。 提供第二通道，用于使第一室与排气入口的上游侧的进气通道连通，并且提供第三通道，用于将第二室与位于节流阀的下游侧的进气通道连通 引擎。 致动器被布置成使得当第一和第二室中的压力差超过预定值时阀打开，从而供应浓的空气 - 燃料混合物。

公开(公告)号：US4476834A

公开(公告)日：1984-10-16

申请号：US382457

申请日：1982-05-26

申请人： Kazuo Nakazato

发明人： Kazuo Nakazato

IPC分类号： F02D41/14 ,  F02M7/24 ,  F02M11/00 ,  F02M11/02 ,  F02B3/00

CPC分类号： F02M11/02 ,  F02D41/1489

摘要： A system for controlling air-fuel ratio of air-fuel mixture for an internal combustion engine having a two-barrel carburetor. The system is provided with an O.sub.2 sensor for detecting the concentration of oxygen in the exhaust gases, an on-off electromagnetic valve for correcting the air-fuel ratio of the air-fuel mixture supplied by the carburetor and an electronic control circuit. The electronic control circuit operates to compare output signal of the detector with a stoichiometric value, and to produce driving pulses for driving the on-off electromagnetic valve and for controlling the air-fuel ratio to a value approximately equal to the stoichiometric air-fuel ratio. A fixed signal generating circuit is selectively connected to the electronic control circuit. The two-barrel carburetor has an actuator actuated by the vacuum at the venturi of the carburetor for opening a throttle valve of the secondary side of the carburetor. A first switch is provided to be operated in response to the actuation of the actuator and connected to a second switch in the control circuit. The second switch connects the fixed signal generating circuit to the electronic control circuit for providing a fixed duty ratio for the valve and renders the electronic control circuit non-responsive to the output of the O.sub.2 sensor.

摘要翻译： 一种用于控制具有双桶化油器的内燃机的空气燃料混合物的空燃比的系统。 该系统设置有用于检测排气中的氧浓度的O2传感器，用于校正由化油器供应的空气燃料混合物的空燃比的开关电磁阀和电子控制电路。 电子控制电路用于将检测器的输出信号与化学计量值进行比较，并产生用于驱动开关电磁阀的驱动脉冲，并将空燃比控制到大致等于理论空燃比的值 。 固定信号发生电路选择性地连接到电子控制电路。 双桶化油器具有由化油器的文丘里管处的真空致动的致动器，用于打开化油器次级侧的节流阀。 提供第一开关以响应于致动器的致动而被操作并连接到控制电路中的第二开关。 第二开关将固定信号发生电路连接到电子控制电路，以提供用于阀的固定占空比，并使电子控制电路对O2传感器的输出无响应。

公开(公告)号：US08129978B2

公开(公告)日：2012-03-06

申请号：US12308769

申请日：2007-07-11

申请人： Kazuo Nakazato

发明人： Kazuo Nakazato

IPC分类号： G01N27/00 ,  G01N27/60 ,  G01N27/62

CPC分类号： G01N27/4148 ,  G01N27/4145

摘要： To realize a small size and high detection accuracy in a substance detection apparatus. A charge detection field effect transistor and a control circuit therefor are provided in each cell, and the control circuit controls the charge detection field effect transistor so that the drain-source voltage and the drain current of the charge detection field effect transistor are always maintained constant. The control circuit may be formed in a CMOS configuration including a small number of elements in a small area using a standard CMOS integrated circuit technique.

摘要翻译： 在物质检测装置中实现小尺寸和高检测精度。 在每个单元中提供电荷检测场效应晶体管及其控制电路，并且控制电路控制电荷检测场效应晶体管，使得电荷检测场效应晶体管的漏源电压和漏极电流始终保持恒定 。 控制电路可以使用标准CMOS集成电路技术形成为包括少量元件的CMOS配置。

公开(公告)号：US20050162894A1

公开(公告)日：2005-07-28

申请号：US11085213

申请日：2005-03-22

申请人： Kiyoo Itoh ,  Kazuo Nakazato

发明人： Kiyoo Itoh ,  Kazuo Nakazato

IPC分类号： G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C16/04 ,  G11C11/24

CPC分类号： G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

摘要翻译： 一种半导体集成电路装置，包括多个存储单元，每个存储单元具有保存在存储MOSFET的栅极中的信息的存储MOSFET;写入晶体管，其将与该信息相对应的写入信息电压提供给栅极存储MOSFET;以及电容器，其具有第一 和第二终端。 字线和数据线与存储器单元耦合。 第一电容器端子与字线之一耦合，第二电容器端子与存储MOSFET的栅极耦合。 在半导体集成电路器件的读取操作中，通过字线从第一电压到大于第一电压的第二电压的转变来提高存储MOSFET的栅极电压。

公开(公告)号：US06876569B2

公开(公告)日：2005-04-05

申请号：US10796023

申请日：2004-03-10

申请人： Kiyoo Itoh ,  Kazuo Nakazato

发明人： Kiyoo Itoh ,  Kazuo Nakazato

IPC分类号： G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C16/04 ,  G11C11/24

CPC分类号： G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

摘要翻译： 一种半导体集成电路装置，包括多个存储单元，每个存储单元具有保存在存储MOSFET的栅极中的信息的存储MOSFET;写入晶体管，其将与该信息相对应的写入信息电压提供给栅极存储MOSFET;以及电容器，其具有第一 和第二终端。 字线和数据线与存储器单元耦合。 第一电容器端子与字线之一耦合，第二电容器端子与存储MOSFET的栅极耦合。 在半导体集成电路器件的读取操作中，通过字线从第一电压到大于第一电压的第二电压的转变来提高存储MOSFET的栅极电压。

公开(公告)号：US20050051805A1

公开(公告)日：2005-03-10

申请号：US10887860

申请日：2004-07-12

申请人： Byong Kim ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Byong Kim ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： B82B1/00 ,  G11C13/02 ,  H01L21/337 ,  H01L21/338 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/74 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/808 ,  H01L29/812 ,  H01L51/30 ,  H01L51/40

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/18 ,  H01L51/002 ,  H01L51/0508 ,  H01L51/0545

摘要： A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.

摘要翻译： 一种晶体管器件，包括源极和漏极区域（S，D），提供源极和漏极区域之间的电荷载流子路径的纳米管结构（2,3）和栅极区域（4）。 纳米管结构具有在栅极区域局部修饰的导带结构。 通过掺杂，用于控制路径中的载流子的通过。 该装置可以用作DRAM中的闪存或存储元件。

公开(公告)号：US06825527B2

公开(公告)日：2004-11-30

申请号：US10454527

申请日：2003-06-05

申请人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： H01L2972

CPC分类号： B82Y10/00 ,  G11C16/02 ,  H01L27/108 ,  H01L29/511 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7888

摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

摘要翻译： 通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。 在断电时，DRAM也会丢失存储在其中的信息。 同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性 绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

公开(公告)号：US06642574B2

公开(公告)日：2003-11-04

申请号：US09727497

申请日：2000-12-04

申请人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

发明人： Hideo Sunami ,  Kiyoo Itoh ,  Toshikazu Shimada ,  Kazuo Nakazato ,  Hiroshi Mizuta

IPC分类号： H01L2972

CPC分类号： B82Y10/00 ,  G11C16/02 ,  H01L27/108 ,  H01L29/511 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7883 ,  H01L29/7888

摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

摘要翻译： 通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。 在断电时，DRAM也会丢失存储在其中的信息。 同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性 绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

公开(公告)号：US06501116B2

公开(公告)日：2002-12-31

申请号：US10026769

申请日：2001-12-27

申请人： Teruaki Kisu ,  Kazuo Nakazato ,  Masahito Takahashi

发明人： Teruaki Kisu ,  Kazuo Nakazato ,  Masahito Takahashi

IPC分类号： H01L2708

CPC分类号： H01L27/108 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052

摘要： Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

摘要翻译： 公开了能够使存储单元尺寸小型化的增益单元结构及其制造方法。 存储单元由读取MIS晶体管和写入MIS晶体管构成。 读取MIS晶体管具有形成在半导体衬底的主表面上的一对n +型半导体区域（源极区域和漏极区域）以及经由第一栅极绝缘膜形成在n +型半导体区域13的路径上的第一栅极电极 。 写入MIS晶体管布置在读取MIS晶体管上，并且具有通过以此顺序层叠下半导体层（源极区），中间半导体层（沟道形成区）和上半导体层（漏极区）而形成的层叠结构 。 写入MIS晶体管具有垂直结构，其中第二栅极经由第二栅极绝缘膜布置在层状结构的两个侧壁上。