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35 条记录 (耗时 0.016 秒)

    Semiconductive ceramic and semiconductive ceramic element using the same
    32.
    发明授权
    Semiconductive ceramic and semiconductive ceramic element using the same 失效
    半导体陶瓷和半导体陶瓷元件使用相同

    公开(公告)号：US6054403A

    公开(公告)日：2000-04-25

    申请号：US174212

    申请日：1998-10-16

    申请人： Yoichi Kawase ,  Akinori Nakayama ,  Satoshi Ueno ,  Terunobu Ishikawa ,  Hideaki Niimi

    发明人： Yoichi Kawase ,  Akinori Nakayama ,  Satoshi Ueno ,  Terunobu Ishikawa ,  Hideaki Niimi

    IPC分类号： C04B35/00 ,  C04B35/50 ,  H01C7/04 ,  H01B1/08 ,  H01C7/10 ,  H03B5/12

    CPC分类号： C04B35/50 ,  H01C7/043

    摘要： A semiconductive ceramic in which the B constant is maintained at about 4000 K or more at elevated temperature to thereby decrease power consumption, and the B constant is lowered less than 4000 K at low temperature so as to avoid unnecessary increase of resistance; as well as a semiconductive ceramic element using the same. The semiconductive ceramic is formed of a lanthanum cobalt oxide, which serves as the primary component, and, as a secondary component, at least one oxide of Li, Na, K, Rb, Cs, Be, Mg, Ca, Sr, Ba, Ni, Cu and Zn. The semiconductive ceramic element is fabricated through use of the semiconductive ceramic and an electrode formed thereon.

    摘要翻译： 一种半导体陶瓷，其中B常数在升高的温度下保持在约4000K或更高，从而降低功耗，并且B常数在低温下降低到低于4000K，以避免不必要的电阻增加; 以及使用其的半导体陶瓷元件。 半导体陶瓷由作为主要成分的氧化镧钴氧化物形成，作为二次成分，可以使用Li，Na，K，Rb，Cs，Be，Mg，Ca，Sr，Ba， Ni，Cu和Zn。 半导体陶瓷元件通过使用半导体陶瓷和形成在其上的电极来制造。

    Chip type varistor
    34.
    发明授权
    Chip type varistor 失效
    片式压敏电阻

    公开(公告)号：US5324986A

    公开(公告)日：1994-06-28

    申请号：US901750

    申请日：1992-06-22

    申请人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    发明人： Yasushi Ueno ,  Akinori Nakayama ,  Kazutaka Nakamura ,  Yasunobu Yoneda ,  Yukio Sakabe ,  Tomoaki Ushiro

    IPC分类号： H01C7/10 ,  H01C7/112 ,  H01L23/053 ,  H01L23/14 ,  H01L23/15

    CPC分类号： H01C7/10 ,  H01C7/112

    摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.

    摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。

    Monolithic type varistor
    35.
    发明授权
    Monolithic type varistor 失效
    单片类型变量

    公开(公告)号：US5119062A

    公开(公告)日：1992-06-02

    申请号：US615369

    申请日：1990-11-19

    申请人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    发明人： Kazutaka Nakamura ,  Hiroaki Taira ,  Tohru Higashi ,  Akinori Nakayama ,  Yasunobu Yoneda ,  Yukio Sakabe

    IPC分类号： H01C7/10

    CPC分类号： H01C7/10

    摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.

    摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。