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1.发明授权Semiconductive ceramic composition and semiconductive ceramic element using the same 有权半导体陶瓷组合物和半导体陶瓷元件使用相同
公开(公告)号：US6090735A
公开(公告)日：2000-07-18
申请号：US167895
申请日：1998-10-07
IPC分类号： C04B35/01 , C04B35/50 , H01B1/08 , H01C7/04 , H01C17/065
CPC分类号： C04B35/01 , C04B35/50 , H01B1/08 , H01C17/06533 , H01C7/043 , H01C7/045 , C04B2235/3217 , C04B2235/3224 , C04B2235/3227 , C04B2235/3229 , C04B2235/3244 , C04B2235/3251 , C04B2235/3256 , C04B2235/3258 , C04B2235/3262 , C04B2235/3272 , C04B2235/3275 , C04B2235/3277 , C04B2235/3293 , C04B2235/3294 , C04B2235/3409 , C04B2235/3418 , C04B2235/446 , C04B2235/447 , C04B2235/96
摘要： A semiconductive ceramic composition having negative resistance-temperature characteristics, wherein the composition comprises lanthanum cobalt oxide as the primary component, and, as secondary components, at least one oxide of an element selected from B, Fe and Al and at least one oxide of an element selected from Si, Zr, Hf, Ta, Sn, Sb, W, Mo, Te, Ce, Nb, Mn, Th and P. A semiconductive ceramic composition having a resistivity of approximately 10 .OMEGA..multidot.cm to 100 .OMEGA..multidot.cm at room temperature is obtained by controlling the amount of additives. Since the resistivity at room temperature can be enhanced to several times or more that of the conventional compositions while characteristics of the conventional compositions are maintained, the composition may be widely applied to control heavy current.
摘要翻译： 一种具有负电阻 - 温度特性的半导体陶瓷组合物，其中所述组合物包含氧化镧钴作为主要组分，并且作为次要组分，选自B，Fe和Al中的至少一种元素的氧化物和至少一种氧化物 选自Si，Zr，Hf，Ta，Sn，Sb，W，Mo，Te，Ce，Nb，Mn，Th和P中的一种元素。在室温下电阻率为约10欧米伽至100欧米伽x厘米的半导体陶瓷组合物 通过控制添加剂的量获得。 由于在保持常规组合物的特性的同时，常规组合物的电阻率可以提高到常规组合物的几倍或更多，因此组合物可广泛用于控制大电流。
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2.发明授权Material and paste for producing internal electrode of varistor, laminated varistor, and method for producing the varistor 有权用于制造变阻器内部电极的材料和糊料，层压变阻器，以及用于制造压敏电阻的方法
公开(公告)号：US6147588A
公开(公告)日：2000-11-14
申请号：US271605
申请日：1999-03-17
申请人： Akinori Nakayama , Ryouichi Urahara , Yukio Sakabe
发明人： Akinori Nakayama , Ryouichi Urahara , Yukio Sakabe
摘要： The present invention provides a varistor which has low variation in electric characteristics and enhanced withstand electrostatic voltage and which can be fired at low temperature; as well as a method for producing the same. The laminated varistor comprises a sintered laminate formed by laminating alternating layers of semiconducting ceramic which comprises ZnO as a primary component and at least Bi oxide as a secondary component, and internal electrodes which predominantly comprise Pt and Pd as an inevitable impurity; and external electrodes maintaining electrical contact with the internal electrodes, wherein the Pd content is controlled to be about 0.1 wt. % or less based on the content of Pt, which is a primary component of the internal electrodes.
摘要翻译： 本发明提供一种变阻器，其电特性变化小，抗静电电压提高，可在低温下烧制; 以及其制造方法。 层叠压敏电阻器包括通过将包含ZnO作为主要成分的交替层和至少Bi氧化物作为次要组分层叠的交替层和主要包含Pt和Pd作为不可避免的杂质的内部电极而形成的烧结层叠体。 以及与内部电极保持电接触的外部电极，其中Pd含量被控制在约0.1wt。 基于作为内部电极的主要成分的Pt的含量的％以下。
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公开(公告)号：US6153931A
公开(公告)日：2000-11-28
申请号：US262573
申请日：1999-03-04
CPC分类号： H01C7/025
摘要： The present invention provides a barium titanate-based semiconducting ceramic which exhibits excellent PTC characteristic and which can be fired at a temperature lower than 1000.degree. C. The present invention also provides an electronic element fabricated from the ceramic. The semiconducting ceramic contains, in a semiconducting sintered barium titanate; boron oxide; an oxide of at least one of barium, strontium, calcium, lead, yttrium and a rare earth element; and an optional oxide of at least one of titanium, tin, zirconium, niobium, tungsten and antimony in which the atomic boron is0.005.ltoreq.B/.beta..ltoreq.0.50 and1.0.ltoreq.B/(.alpha.-.beta.).ltoreq.4.0wherein .alpha. represents the total number of atoms of barium, strontium, calcium, lead, yttrium and rare earth element contained in the semiconducting ceramic, and .beta. represents the total number of atoms of titanium, tin, zirconium, niobium, tungsten and antimony contained in the semiconducting ceramic.
摘要翻译： 本发明提供一种钛酸钡系半导体陶瓷，其表现出优异的PTC特性，并可在低于1000℃的温度下烧制。本发明还提供了由陶瓷制成的电子元件。 半导体陶瓷在半导体烧结的钛酸钡中含有; 氧化硼 钡，锶，钙，铅，钇和稀土元素中的至少一种的氧化物; 和钛，锡，锆，铌，钨和锑中的至少一种的任选的氧化物，其中原子硼为0.005≤B/β= 0.50和1.0
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公开(公告)号：US06222262B1
公开(公告)日：2001-04-24
申请号：US09453994
申请日：1999-12-03
IPC分类号： H01L710
CPC分类号： H01C7/043
摘要： A semiconductor ceramic device includes a semiconductor ceramic sintered body and external electrodes. The semiconductor ceramic sintered body contains a lanthanum cobalt type oxide major component, about 0.1 to 10 mol % on an element conversion basis of an oxide of Cr as a sub-component, and about 0.001 to 0.5 mol % on an element conversion basis of at least one of the oxides of Li, Na, K, Rb, Cs, Be, Mg, Ca, Sr, Ba, Ni, Cu and Zn.
摘要翻译： 半导体陶瓷器件包括半导体陶瓷烧结体和外部电极。 半导体陶瓷烧结体含有镧钴型氧化物主成分，以作为副成分的Cr的氧化物的元素换算率为约0.1〜10摩尔％，以元素换算为基准的约0.001〜0.5摩尔％ Li，Na，K，Rb，Cs，Be，Mg，Ca，Sr，Ba，Ni，Cu和Zn的氧化物中的至少一种。
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5.发明授权Semiconducting ceramic compounds having negative resistance-temperature characteristics with critical temperatures 失效具有临界温度的负电阻 - 温度特性的半导体陶瓷化合物
公开(公告)号：US5858902A
公开(公告)日：1999-01-12
申请号：US831722
申请日：1997-04-01
摘要： A semiconducting ceramic having negative resistance-temperature characteristics and a critical temperature consisting essentially of a rare-earth transition element oxide which is an oxide of a combination of samarium and nickel, wherein the samarium is partially replaced with Ln which is at least one other element selected from the group consisting of bismuth and rare-earth elements excluding lanthanum and cerium.
摘要翻译： 一种具有负电阻温度特性和临界温度的半导体陶瓷，其基本上由作为钐和镍组合的氧化物的稀土过渡元素氧化物组成，其中钐部分被Ln替代，Ln是至少一种其它元素 选自不含镧和铈的铋和稀土元素组成的组。
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6.发明授权Semiconductive ceramic composition and semiconductive ceramic device using the same 失效半导体陶瓷组合物和半导体陶瓷器件使用相同
公开(公告)号：US5703000A
公开(公告)日：1997-12-30
申请号：US796916
申请日：1997-02-06
CPC分类号： H01C7/043
摘要： Provided is a semiconductive ceramic composition comprising a lanthanum cobalt oxide and having a negative resistance-temperature characteristic, which contains, as the side component, a chromium oxide in an amount of from about 0.005 to 30 mol % in terms of chromium, and also a semiconductive ceramic device comprising the composition. The device is usable for rush current inhibition, for motor start-up retardation and for halogen lamp protection, and is also usable in temperature-compensated crystal oscillators.
摘要翻译： 本发明提供一种包含氧化镧钴并具有负电阻温度特性的半导体陶瓷组合物，其含有以铬计为0.005〜30摩尔％左右的铬氧化物作为副成分， 包含该组合物的半导体陶瓷装置。 该装置可用于冲击电流抑制，电机启动延迟和卤素灯保护，也可用于温度补偿晶体振荡器。
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7.发明授权
公开(公告)号：US6054403A
公开(公告)日：2000-04-25
申请号：US174212
申请日：1998-10-16
摘要： A semiconductive ceramic in which the B constant is maintained at about 4000 K or more at elevated temperature to thereby decrease power consumption, and the B constant is lowered less than 4000 K at low temperature so as to avoid unnecessary increase of resistance; as well as a semiconductive ceramic element using the same. The semiconductive ceramic is formed of a lanthanum cobalt oxide, which serves as the primary component, and, as a secondary component, at least one oxide of Li, Na, K, Rb, Cs, Be, Mg, Ca, Sr, Ba, Ni, Cu and Zn. The semiconductive ceramic element is fabricated through use of the semiconductive ceramic and an electrode formed thereon.
摘要翻译： 一种半导体陶瓷，其中B常数在升高的温度下保持在约4000K或更高，从而降低功耗，并且B常数在低温下降低到低于4000K，以避免不必要的电阻增加; 以及使用其的半导体陶瓷元件。 半导体陶瓷由作为主要成分的氧化镧钴氧化物形成，作为二次成分，可以使用Li，Na，K，Rb，Cs，Be，Mg，Ca，Sr，Ba， Ni，Cu和Zn。 半导体陶瓷元件通过使用半导体陶瓷和形成在其上的电极来制造。
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公开(公告)号：US5324986A
公开(公告)日：1994-06-28
申请号：US901750
申请日：1992-06-22
申请人： Yasushi Ueno , Akinori Nakayama , Kazutaka Nakamura , Yasunobu Yoneda , Yukio Sakabe , Tomoaki Ushiro
发明人： Yasushi Ueno , Akinori Nakayama , Kazutaka Nakamura , Yasunobu Yoneda , Yukio Sakabe , Tomoaki Ushiro
IPC分类号： H01C7/10 , H01C7/112 , H01L23/053 , H01L23/14 , H01L23/15
摘要： A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.
摘要翻译： 一种芯片型变阻器，其中第一和第二内部电极嵌入在通过层叠多个半导体陶瓷层而不是在陶瓷层的厚度方向上彼此不重叠而获得的烧结体中， 第一和第二内部电极被引出到烧结体彼此相对的一对侧表面中的一个和另一个，并且分别与形成在烧结体的一对侧表面上的外部电极电连接， 不与上述外部电极电连接的连接型内部电极嵌入在烧结体中，非连接型内部电极配置成与第一和第二内部电极重叠，同时被 半导体陶瓷层。
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公开(公告)号：US5119062A
公开(公告)日：1992-06-02
申请号：US615369
申请日：1990-11-19
申请人： Kazutaka Nakamura , Hiroaki Taira , Tohru Higashi , Akinori Nakayama , Yasunobu Yoneda , Yukio Sakabe
发明人： Kazutaka Nakamura , Hiroaki Taira , Tohru Higashi , Akinori Nakayama , Yasunobu Yoneda , Yukio Sakabe
IPC分类号： H01C7/10
CPC分类号： H01C7/10
摘要： A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer. The value of the number of grain boundaries between semiconductor particles in at least one semiconductor ceramic layer is two or less.
摘要翻译： 一种单片型压敏电阻，其中多个内部电极被布置在由半导体陶瓷组成的烧结体中，以便在被半导体陶瓷层分离的同时彼此重叠。 多个内部电极电连接到形成在烧结体的两个端面上的第一和第二外部电极。 一个或多个非连接型内部电极布置在多个内部电极的相邻的内部电极之间，并且不与外部电极电连接，每个非连接型内部电极与每个相邻的内部电极或非电连接的内部电极间隔开， 连接型内部电极，同时由半导体陶瓷层分离。 通过在内部电极和半导体陶瓷层的界面处形成的肖特基势垒以及非连接型内部电极和半导体陶瓷层的界面获得电压非线性。 至少一个半导体陶瓷层中的半导体粒子之间的晶界数的值为2以下。
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10.发明申请公开(公告)号：US20120081206A1
公开(公告)日：2012-04-05
申请号：US13326706
申请日：2011-12-15
申请人： Atsushi Kishimoto , Wataru Aoto , Akinori Nakayama
发明人： Atsushi Kishimoto , Wataru Aoto , Akinori Nakayama
CPC分类号： H01C7/025 , C04B35/4682 , C04B2235/3208 , C04B2235/3258 , C04B2235/77 , C04B2235/79 , H01C17/06533
摘要： A semiconductor ceramic and a positive-coefficient characteristic thermistor are provided which have a stable PTC characteristic, a high double point, and a wide operating temperature range. The semiconductor ceramic contains, as a main component, a barium titanate-based composition having a perovskite structure expressed by a general formula AmBO3. Out of 100 mol % of the Ti, an amount in a range of 0.05 mol % or more to 0.3 mol % or less of Ti is replaced with W as a semiconductor forming agent, the ratio m of A sites mainly to B sites is 0.99≦m≦1.002, and an actually-measured sintered density is 70% or more and 90% or less of the theoretical sintered density. In the positive-coefficient characteristic thermistor, a component body is formed of the semiconductor ceramic.
摘要翻译： 提供了具有稳定的PTC特性，高双点和宽工作温度范围的半导体陶瓷和正系数特性热敏电阻。 半导体陶瓷作为主要成分含有具有由通式AmBO 3表示的钙钛矿结构的钛酸钡类组合物。 在100摩尔％的Ti中，作为半导体形成剂的W被替换为0.05摩尔％以上至0.3摩尔％以下的Ti的量，作为主要部位的A部位的比例m为0.99 ＆nlE; m＆nlE; 1.002，实际测量的烧结密度为理论烧结密度的70％以上且90％以下。 在正系数特性热敏电阻中，由半导体陶瓷形成元件体。
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