公开(公告)号：US20120163103A1

公开(公告)日：2012-06-28

申请号：US12976630

申请日：2010-12-22

申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US20100164001A1

公开(公告)日：2010-07-01

申请号：US12319015

申请日：2008-12-30

申请人： Joodong Park ,  Chia-Hong Jan ,  Lisa M. McGill

发明人： Joodong Park ,  Chia-Hong Jan ,  Lisa M. McGill

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/22

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/665 ,  H01L29/66575

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting an exposed p type silicon portion of a substrate with a carbon species, wherein endcap regions of a blocked salicide resistor and a p type structure that are both disposed on the exposed p type silicon portion of the substrate are implanted with the carbon species.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括用碳物种植入衬底的暴露的p型硅部分，其中嵌入在衬底的暴露的p型硅部分上的封闭的自对夹硅电阻器和ap型结构的端盖区域被植入碳 种类。

公开(公告)号：US20100163952A1

公开(公告)日：2010-07-01

申请号：US12347904

申请日：2008-12-31

申请人： Chia-Hong Jan ,  Walid M. Hafez

发明人： Chia-Hong Jan ,  Walid M. Hafez

IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L21/04 ,  H01L29/41

CPC分类号： H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.

摘要翻译： 描述了具有集成的高k电介质层和金属控制栅极的半导体器件。 对其制造方法进行说明。 半导体器件的实施例包括设置在浮置栅极上的高k电介质层。 高k电介质层限定凹陷。 金属控制门形成在凹槽中。

公开(公告)号：US20090170273A1

公开(公告)日：2009-07-02

申请号：US12005944

申请日：2007-12-27

申请人： Joodong Park ,  Chia-Hong Jan ,  Paul Reese

发明人： Joodong Park ,  Chia-Hong Jan ,  Paul Reese

IPC分类号： H01L21/02

CPC分类号： H01L29/8605 ,  H01L28/24

摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.

摘要翻译： 通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。 氧化物层在衬底上。 在氧化物层上形成氮化物层并进行退火。 在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。 使用抗蚀剂层作为图案蚀刻退火的氮化物层。 去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。 将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

公开(公告)号：US07436035B2

公开(公告)日：2008-10-14

申请号：US10917722

申请日：2004-08-12

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L29/72

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US07211872B2

公开(公告)日：2007-05-01

申请号：US09477764

申请日：2000-01-04

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack within inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔件内部间隔堆叠和薄的外部间隔件。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06765273B1

公开(公告)日：2004-07-20

申请号：US09115405

申请日：1998-07-14

申请人： Robert S. Chau ,  Ebrahim Andideh ,  Mitch C. Taylor ,  Chia-Hong Jan ,  Julie Tsai

发明人： Robert S. Chau ,  Ebrahim Andideh ,  Mitch C. Taylor ,  Chia-Hong Jan ,  Julie Tsai

IPC分类号： H01L2976

CPC分类号： H01L29/66515 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823878 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

公开(公告)号：US06593633B2

公开(公告)日：2003-07-15

申请号：US09477869

申请日：2000-01-05

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。

公开(公告)号：US06518155B1

公开(公告)日：2003-02-11

申请号：US08884912

申请日：1997-06-30

申请人： Robert S. Chau ,  Ebrahim Andideh ,  Mitch C. Taylor ,  Chia-Hong Jan ,  Julie Tsai

发明人： Robert S. Chau ,  Ebrahim Andideh ,  Mitch C. Taylor ,  Chia-Hong Jan ,  Julie Tsai

IPC分类号： H01L213205

CPC分类号： H01L29/66515 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823878 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

公开(公告)号：US06509618B2

公开(公告)日：2003-01-21

申请号：US09476920

申请日：2000-01-04

申请人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

发明人： Chia-Hong Jan ,  Julie A. Tsai ,  Simon Yang ,  Tahir Ghani ,  Kevin A. Whitehill ,  Steven J. Keating ,  Alan Myers

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/82345 ,  H01L29/4933 ,  H01L29/66575 ,  Y10S257/90

摘要： A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

摘要翻译： 一种在0.20μm以下提高多晶硅门禁耐化学性的方法和装置。 本发明的几个实施例提供了具有凹入和部分凹入间隔件的栅电极结构的形成。 一个实施例提供具有凹入的厚内部间隔件和厚的外部间隔件的栅电极结构。 另一个实施例提供具有凹陷的薄内部间隔件和凹入的厚的外部间隔件的栅极电极结构。 另一实施例提供具有薄的内部间隔件和部分凹入的外部间隔件的栅电极结构。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 内部间隔物堆叠，内部具有薄的隔离物和薄的隔离物。 另一实施例提供具有两个间隔堆叠的栅电极结构。 最外面的间隔物堆叠有凹陷的细内部间隔物和凹陷的厚的外部间隔物。 具有凹陷的细内部间隔件和凹陷的细外部间隔件的内部间隔件堆叠。