公开(公告)号：US11727993B2

公开(公告)日：2023-08-15

申请号：US17864674

申请日：2022-07-14

申请人： Kioxia Corporation

发明人： Hiroshi Maejima

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C5/02 ,  G11C5/06 ,  G11C16/08 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3422

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

公开(公告)号：US11705443B2

公开(公告)日：2023-07-18

申请号：US17012111

申请日：2020-09-04

申请人： Kioxia Corporation

发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Nobuaki Okada ,  Hiroshi Nakamura ,  Takahiro Tsurudo

IPC分类号： H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US11594285B2

公开(公告)日：2023-02-28

申请号：US17481892

申请日：2021-09-22

申请人： Kioxia Corporation

发明人： Takeshi Hioka ,  Tsukasa Kobayashi ,  Koji Kato ,  Yuki Shimizu ,  Hiroshi Maejima

IPC分类号： G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11568 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/30

摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US20220301615A1

公开(公告)日：2022-09-22

申请号：US17472361

申请日：2021-09-10

申请人： Kioxia Corporation

发明人： Hiroshi Maejima

IPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06

摘要： According to one embodiment, a semiconductor memory device includes a first bit line extending in a first direction and coupled to a first memory cell, a first pad coupled to the first bit line, a first sense amplifier coupled to the first pad, a second bit line being adjacent to the first bit line and extending in the first direction and coupled to a second memory cell, a second pad coupled to the second bit line, and a second sense amplifier coupled to the second pad. The first and second sense amplifiers are adjacent to each other and are arranged in a second direction intersecting the first direction. The first and second pads are adjacent to each other and are arranged in a third direction intersecting the first direction and the second direction.