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    Semiconductor storage device
    2.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US11600328B2

    公开(公告)日：2023-03-07

    申请号：US17591216

    申请日：2022-02-02

    申请人： KIOXIA CORPORATION

    发明人： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

    IPC分类号： G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

    摘要： A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

    Semiconductor storage device
    3.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US11276466B2

    公开(公告)日：2022-03-15

    申请号：US16952858

    申请日：2020-11-19

    申请人： KIOXIA CORPORATION

    发明人： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

    IPC分类号： G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

    摘要： A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11996143B2

    公开(公告)日：2024-05-28

    申请号：US17846889

    申请日：2022-06-22

    申请人： KIOXIA CORPORATION

    发明人： Tomoki Nakagawa ,  Koji Kato ,  Toshifumi Hashimoto

    IPC分类号： G11C16/30 ,  G11C5/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    CPC分类号： G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

    摘要： A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11894074B2

    公开(公告)日：2024-02-06

    申请号：US17469812

    申请日：2021-09-08

    申请人： Kioxia Corporation

    发明人： Koji Kato

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/10

    CPC分类号： G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

    摘要： A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11810624B2

    公开(公告)日：2023-11-07

    申请号：US17473293

    申请日：2021-09-13

    申请人： Kioxia Corporation

    发明人： Koji Kato

    IPC分类号： G11C5/02 ,  G11C16/26 ,  G11C16/32 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

    摘要： A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.