公开(公告)号：US20080116506A1

公开(公告)日：2008-05-22

申请号：US11756559

申请日：2007-05-31

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract translation: 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US20080087942A1

公开(公告)日：2008-04-17

申请号：US11785322

申请日：2007-04-17

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L29/792 ,  G11C11/34 ,  H01L21/336

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785 ,  H01L29/792

Abstract: A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

Abstract translation: 提供了包括基板，通道，多层结构，栅极，第一端子和第二端子的垂直沟道存储器。 通道从基板突出并具有顶表面和两个垂直表面。 多层结构设置在通道的两个垂直表面上。 栅极跨层多层结构位于通道的两个垂直表面上方。 第一端子和第二端子分别位于与栅极相对的通道的两侧。

公开(公告)号：US20080079064A1

公开(公告)日：2008-04-03

申请号：US11898528

申请日：2007-09-13

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Abstract translation: 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

Applicant: Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

Inventor： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC: G11C11/34 ,  H01L21/36

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract translation: 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07315474B2

公开(公告)日：2008-01-01

申请号：US11324581

申请日：2006-01-03

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/265 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

Abstract translation: 存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有小的空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且描述设置在绝缘层上方的栅极电极及其阵列和操作方法。

公开(公告)号：US20070258289A1

公开(公告)日：2007-11-08

申请号：US11381760

申请日：2006-05-05

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

Abstract: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

Abstract translation: 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

公开(公告)号：US20070037328A1

公开(公告)日：2007-02-15

申请号：US11203087

申请日：2005-08-15

Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US20060205157A1

公开(公告)日：2006-09-14

申请号：US11429070

申请日：2006-05-05

Applicant: Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

Inventor： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

Abstract translation: 提供非易失性存储器。 存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。 字线设置在基板上，与埋入位线交叉。

公开(公告)号：US07067375B1

公开(公告)日：2006-06-27

申请号：US11018507

申请日：2004-12-20

Applicant: Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

Inventor： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

公开(公告)号：US09082656B2

公开(公告)日：2015-07-14

申请号：US13294852

申请日：2011-11-11

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11578

Abstract: A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

Abstract translation: 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。